soc/intel/common/block: Move common uart function to block/uart

This patch moves uart functions which are common across multiple soc to
block/uart. This will remove redundant code copy from soc
{skylake/apollolake/cannonlake}.

BUG=b:78109109
BRANCH=none
TEST=Build and boot on KBL/APL/CNL platform.

Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

5 files changed, 49 insertions, 89 deletions

diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c
index b7e77976b0..0aac186b42 100644
--- a/src/soc/intel/cannonlake/bootblock/bootblock.c
+++ b/src/soc/intel/cannonlake/bootblock/bootblock.c
@@ -15,6 +15,7 @@
 
 #include <bootblock_common.h>
 #include <intelblocks/gspi.h>
+#include <intelblocks/uart.h>
 #include <soc/bootblock.h>
 #include <soc/iomap.h>
 #include <soc/pch.h>
@@ -31,8 +32,8 @@ void bootblock_soc_early_init(void)
 	bootblock_pch_early_init();
 	bootblock_cpu_init();
 	pch_early_iorange_init();
-	if (IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM))
-		pch_uart_init();
+	if (IS_ENABLED(CONFIG_UART_DEBUG))
+		uart_bootblock_init();
 }
 
 void bootblock_soc_init(void)
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index eb67012781..033f69aaf5 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -80,6 +80,7 @@ void bootblock_pch_early_init(void)
 	gspi_early_bar_init();
 	p2sb_enable_bar();
 	p2sb_configure_hpet();
+
 	/*
 	 * Enabling PWRM Base for accessing
 	 * Global Reset Cause Register.
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h
index 75f11c0eee..ed9b29ffee 100644
--- a/src/soc/intel/cannonlake/include/soc/iomap.h
+++ b/src/soc/intel/cannonlake/include/soc/iomap.h
@@ -29,11 +29,13 @@
 #define PCH_TRACE_HUB_BASE_ADDRESS	0xfc800000
 #define PCH_TRACE_HUB_BASE_SIZE	0x00800000
 
-#define UART_DEBUG_BASE_0_SIZE	0x1000
+#define UART_BASE_SIZE		0x1000
+
 #define UART_BASE_0_ADDRESS	0xfe032000
 /* Both UART BAR 0 and 1 are 4KB in size */
 #define UART_BASE_0_ADDR(x)	(UART_BASE_0_ADDRESS + (2 * \
-					UART_DEBUG_BASE_0_SIZE * (x)))
+					UART_BASE_SIZE * (x)))
+#define UART_BASE(x)		UART_BASE_0_ADDR(x)
 
 #define EARLY_I2C_BASE_ADDRESS	0xfe040000
 #define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h
index 53dd66a908..da64a7a88f 100644
--- a/src/soc/intel/cannonlake/include/soc/pch.h
+++ b/src/soc/intel/cannonlake/include/soc/pch.h
@@ -29,6 +29,5 @@
 #define PCIE_CLK_FREE			0x80
 
 void pch_log_state(void);
-void pch_uart_init(void);
 
 #endif
diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c
index 80404100fe..d03d21e3c1 100644
--- a/src/soc/intel/cannonlake/uart.c
+++ b/src/soc/intel/cannonlake/uart.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2017 Intel Corporation
+ * Copyright (C) 2017-2018 Intel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,116 +14,73 @@
  */
 
 #include <assert.h>
-#include <cbmem.h>
-#include <console/uart.h>
-#include <device/pci.h>
 #include <device/pci_def.h>
 #include <intelblocks/gpio.h>
 #include <intelblocks/lpss.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/uart.h>
 #include <soc/iomap.h>
-#include <soc/nvs.h>
 #include <soc/pch.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
+#include <string.h>
 
-#if !ENV_RAMSTAGE
 /* Serial IO UART controller legacy mode */
 #define PCR_SERIAL_IO_GPPRVRW7		0x618
 #define PCR_SIO_PCH_LEGACY_UART(idx)	(1 << (idx))
 
-static const struct port {
-	struct pad_config pads[2]; /* just TX and RX */
-#if defined(__SIMPLE_DEVICE__)
-	pci_devfn_t dev;
-#else
-	struct device *dev;
-#endif
-} uart_ports[] = {
-	{.dev = PCH_DEV_UART0,
-	 .pads = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* RX */
-		   PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1)} /* TX */
+const struct uart_gpio_pad_config uart_gpio_pads[] = {
+	{
+		.console_index = 0,
+		.gpios = {
+			PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */
+			PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */
+		},
 	},
-	{.dev = PCH_DEV_UART1,
-	 .pads = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* RX */
-		   PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1)} /* TX */
+	{
+		.console_index = 1,
+		.gpios = {
+			PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */
+			PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */
+		},
 	},
-	{.dev = PCH_DEV_UART2,
-	 .pads = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* RX */
-		   PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1)} /* TX */
+	{
+		.console_index = 2,
+		.gpios = {
+			PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */
+			PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */
+		},
 	}
 };
 
-void pch_uart_init(void)
-{
-	uintptr_t base;
-	const struct port *p;
-
-	assert(CONFIG_UART_FOR_CONSOLE < ARRAY_SIZE(uart_ports));
-	p = &uart_ports[CONFIG_UART_FOR_CONSOLE];
-	base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
-
-	uart_common_init(p->dev, base);
+const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
 
-	/* Put UART2 in byte access mode for 16550 compatibility */
-	if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {
-		pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
-			PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
-
-		/*
-		 * Dummy read after setting any of GPPRVRW7.
-		 * Required for UART 16550 8-bit Legacy mode to become active
-		 */
-		lpss_clk_read(base);
-	}
-
-	gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads));
-}
-#endif
-
-#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
-uintptr_t uart_platform_base(int idx)
+void soc_uart_set_legacy_mode(void)
 {
-	/* We can only have one serial console at a time */
-	return UART_BASE_0_ADDR(idx);
+	pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
+		PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
+	/*
+	 * Dummy read after setting any of GPPRVRW7.
+	 * Required for UART 16550 8-bit Legacy mode to become active
+	 */
+	lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE));
 }
-#endif
 
-device_t pch_uart_get_debug_controller(void)
+struct device *soc_uart_console_to_device(int uart_console)
 {
-	switch (CONFIG_UART_FOR_CONSOLE) {
+	/*
+	 * if index is valid, this function will return corresponding structure
+	 * for uart console else will return NULL.
+	 */
+	switch (uart_console) {
 	case 0:
-		return PCH_DEV_UART0;
+		return (struct device *)PCH_DEV_UART0;
 	case 1:
-		return PCH_DEV_UART1;
+		return (struct device *)PCH_DEV_UART1;
 	case 2:
+		return (struct device *)PCH_DEV_UART2;
 	default:
-		return PCH_DEV_UART2;
-	}
-}
-
-void pch_uart_read_resources(struct device *dev)
-{
-	pci_dev_read_resources(dev);
-
-	/* Set the configured UART base address for the debug port */
-	if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) {
-		struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
-		/* Need to set the base and size for the resource allocator. */
-		res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE);
-		res->size = UART_DEBUG_BASE_0_SIZE;
-		res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
-			IORESOURCE_FIXED;
+		printk(BIOS_ERR, "Invalid UART console index\n");
+		return NULL;
 	}
 }
-
-bool pch_uart_init_debug_controller_on_resume(void)
-{
-	global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-
-	if (gnvs)
-		return !!gnvs->uior;
-
-	return false;
-}