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| author | Subrata Banik <subratabanik@google.com> | 2022-04-18 13:43:40 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-27 12:36:31 +0000 |
| commit | a9989989e3e30c84d8951ad4a37ea79816847ac6 (patch) | |
| tree | 3e1134380acf8aaf8c0d8e863691746a400f99bc /src/soc/intel/cannonlake | |
| parent | 71fd0fa78008151286ce7b341f31b5cec0ff6553 (diff) | |
soc/intel/alderlake: Skip FSP Notify API (post PCI enumeration)
Alder Lake SoC deselects USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM Kconfig
to skip FSP notify API (Post PCI Enumeration) and make use of native
coreboot driver to perform SoC recommended operations prior booting to
payload/OS.
BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects required configs.
[INFO ] coreboot skipped calling FSP notify phase: 00000020.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I46f6ca791fb60b417d205d0a54705f3481deebd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
0 files changed, 0 insertions, 0 deletions