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authorPaul Fagerburg <pfagerburg@chromium.org>2019-07-12 10:21:35 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-07-25 16:05:32 +0000
commit877481cda24aa179da5ea1ad437198d4df26dec1 (patch)
treecec96eb51475f2539cee94bc5fbdbcf9e97404b9 /src/soc/intel/cannonlake
parentdeab64d2b699ad711c8f7f71b9aae40c7bd31329 (diff)
soc/intel/cannonlake: Split the "internal PME" wake-up into more detail
The "internal PME" wake-up source could be from integrated LAN, HD audio/audio DSP, SATA, XHCI, CNVi, or an ME maskable host wake. chromium:1680839 adds USB port details to the wake-up when the XHCI causes the wake-up. Expand the logging for wake-up details to identify and log the other wake-up sources with more details. Note that wake on Integrated LAN (GbE), SATA, and ME Maskable Host Wake are not in use on Hatch, so these will not be tested. BUG=b:128936450 BRANCH=none TEST=``FW_NAME=hatch emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`` Ensure /build/hatch/firmware/image-hatch.serial.bin has been built. Program image-hatch.serial.bin into the DUT using flashrom. Switch the DUT to the console (Ctrl-Alt-F2, or use the AP console via servo). XHCI USB 2.0 * Plug a USB keyboard into a USB-A port * ``powerd_dbus_suspend`` * Verify low power mode by issuing the ``powerinfo`` command on the EC console (via servo). Expect to see ``power state 4 = S0ix``. * Press a key on the USB keyboard * ``mosys eventlog list`` shows: 12 | 2019-06-26 14:52:23 | S0ix Enter 13 | 2019-06-26 14:53:07 | S0ix Exit 14 | 2019-06-26 14:53:07 | Wake Source | PME - XHCI (USB 2.0 port) | 3 15 | 2019-06-26 14:53:07 | Wake Source | GPE # | 109 CNVi (connected to Wi-Fi): * Enable wake on disconnect via ``iw phy0 wowlan enable disconnect`` * Set up a hotspot on an Android phone * Connect the Chromebook to th hotspot * ``powerd_dbus_suspend`` * Verify low power mode by issuing the ``powerinfo`` command on the EC console (via servo). Expect to see ``power state 4 = S0ix``. * Turn off the hotspot on the phone * ``mosys eventlog list`` shows: 8 | 2019-07-11 10:58:17 | S0ix Enter 9 | 2019-07-11 10:59:17 | S0ix Exit 10 | 2019-07-11 10:59:17 | Wake Source | PME - WIFI | 0 11 | 2019-07-11 10:59:17 | Wake Source | GPE # | 109 XHCI USB 3.0 * TBD HD Audio * TBD Change-Id: I2c71f6a56b4e1658a7427f67fa78af773b97ec7f Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34289 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/elog.c82
1 files changed, 81 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c
index 0bccdb7880..a2c359fe10 100644
--- a/src/soc/intel/cannonlake/elog.c
+++ b/src/soc/intel/cannonlake/elog.c
@@ -17,6 +17,7 @@
#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
+#include <device/pci_ops.h>
#include <stdint.h>
#include <elog.h>
#include <intelblocks/pmclib.h>
@@ -24,6 +25,85 @@
#include <soc/pci_devs.h>
#include <soc/pm.h>
+struct pme_status_info {
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
+ uint8_t reg_offset;
+ uint32_t elog_event;
+};
+
+#define PME_STS_BIT (1 << 15)
+
+static void pch_log_add_elog_event(const struct pme_status_info *info)
+{
+ /*
+ * If wake source is XHCI, check for detailed wake source events on
+ * USB2/3 ports.
+ */
+ if ((info->dev == PCH_DEV_XHCI) &&
+ pch_xhci_update_wake_event(soc_get_xhci_usb_info()))
+ return;
+
+ elog_add_event_wake(info->elog_event, 0);
+}
+
+static void pch_log_pme_internal_wake_source(void)
+{
+ size_t i;
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
+ uint16_t val;
+ bool dev_found = false;
+
+ struct pme_status_info pme_status_info[] = {
+ { PCH_DEV_HDA, 0x54, ELOG_WAKE_SOURCE_PME_HDA },
+ { PCH_DEV_GBE, 0xcc, ELOG_WAKE_SOURCE_PME_GBE },
+ { PCH_DEV_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA },
+ { PCH_DEV_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE },
+ { PCH_DEV_XHCI, 0x74, ELOG_WAKE_SOURCE_PME_XHCI },
+ { PCH_DEV_USBOTG, 0x84, ELOG_WAKE_SOURCE_PME_XDCI },
+ /*
+ * The power management control/status register is not
+ * listed in the cannonlake PCH EDS. We have been told
+ * that the PMCS register is at offset 0xCC.
+ */
+ { PCH_DEV_CNViWIFI, 0xcc, ELOG_WAKE_SOURCE_PME_WIFI },
+ };
+
+ for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) {
+ dev = pme_status_info[i].dev;
+ if (!dev)
+ continue;
+
+ val = pci_read_config16(dev, pme_status_info[i].reg_offset);
+
+ if ((val == 0xFFFF) || !(val & PME_STS_BIT))
+ continue;
+
+ pch_log_add_elog_event(&pme_status_info[i]);
+ dev_found = true;
+ }
+
+ /*
+ * If device is still not found, but the wake source is internal PME,
+ * try probing XHCI ports to see if any of the USB2/3 ports indicate
+ * that it was the wake source. This path would be taken in case of GSMI
+ * logging with S0ix where the pci_pm_resume_noirq runs and clears the
+ * PME_STS_BIT in controller register.
+ */
+ if (!dev_found)
+ dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info());
+
+ if (!dev_found)
+ elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
+}
+
static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
{
int i;
@@ -56,7 +136,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps)
/* XHCI - "Power Management Event Bus 0" events include XHCI */
if (ps->gpe0_sts[GPE_STD] & PME_B0_STS)
- pch_xhci_update_wake_event(soc_get_xhci_usb_info());
+ pch_log_pme_internal_wake_source();
/* SMBUS Wake */
if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)