soc/intel: deduplicate ACPI timer emulation

The code for enabling ACPI timer emulation is the same for the SoCs
SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to
common code.

APL differs in not having the delay settings. However, the bits are
marked as "spare" and BWG mentions there are no "reserved bit checks
done". Thus, we can write them unconditionally without any effect.

Note: The ACPI timer emulation can only be used by SoCs with microcode
supporting CTC (Common Timer Copy) / ACPI timer emulation.

Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

1 files changed, 0 insertions, 25 deletions

diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index 20da942f84..61b19894eb 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -14,7 +14,6 @@
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
-#include <soc/pm.h>
 #include <soc/systemagent.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/intel/microcode.h>
@@ -58,29 +57,6 @@ static void configure_misc(void)
 	wrmsr(MSR_POWER_CTL, msr);
 }
 
-/*
- * The emulated ACPI timer allows replacing of the ACPI timer
- * (PM1_TMR) to have no impart on the system.
- */
-static void enable_pm_timer_emulation(void)
-{
-	msr_t msr;
-
-	if (!CONFIG_CPU_XTAL_HZ)
-		return;
-
-	/*
-	 * The derived frequency is calculated as follows:
-	 * (clock * msr[63:32]) >> 32 = target frequency.
-	 * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
-	 */
-	msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
-	/* Set PM1 timer IO port and enable */
-	msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
-			EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
-	wrmsr(MSR_EMULATE_PM_TIMER, msr);
-}
-
 static void configure_c_states(void)
 {
 	msr_t msr;
@@ -135,7 +111,6 @@ void soc_core_init(struct device *cpu)
 
 	set_aesni_lock();
 
-	/* Enable ACPI Timer Emulation via MSR 0x121 */
 	enable_pm_timer_emulation();
 
 	/* Enable Direct Cache Access */