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authorEdward O'Callaghan <quasisec@google.com>2020-06-23 15:49:14 +1000
committerEdward O'Callaghan <quasisec@chromium.org>2020-06-25 04:21:10 +0000
commit28da35417bcde79edbf826fef7d02bbfe5c714cf (patch)
tree5b82b2771cb92197ef44dc8064b710bac92b94b7 /src/soc/intel/cannonlake
parentf9d3d33a55f83661057125223b762ac5cf92401d (diff)
soc/intel/cannonlake: Add missing USB_PORT_WAKE_ENABLE define
Align support for enable wake-on-usb attach/detach as was introduced in Skylake in `commit 3bfe3404df32ca226c624be0435c640bf1ebeae7`. BUG=b:159187889 BRANCH=none TEST=none Change-Id: Ie63e4f1fcdea130f8faed5c0d34a6a96759946b6 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42716 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/include/soc/usb.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/usb.h b/src/soc/intel/cannonlake/include/soc/usb.h
index 247b0ba554..ac5776cab8 100644
--- a/src/soc/intel/cannonlake/include/soc/usb.h
+++ b/src/soc/intel/cannonlake/include/soc/usb.h
@@ -136,4 +136,11 @@ struct usb3_port_config {
.tx_downscale_amp = 0x00, \
}
+/*
+ * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds
+ * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to
+ * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits.
+ */
+#define USB_PORT_WAKE_ENABLE(x) (1 << (x - 1))
+
#endif