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authorPatrick Rudolph <patrick.rudolph@9elements.com>2020-12-14 16:18:04 +0100
committerHung-Te Lin <hungte@chromium.org>2020-12-17 06:22:55 +0000
commit2031221fbda5100556933fb225f9199b88aeebac (patch)
treed3d2d32efb89160cb1f3bb51e33df0f57f405700 /src/soc/intel/cannonlake
parent8b56c8c6b2694500318eba14e291a0586837ebe8 (diff)
soc/intel/cannonlake: Change mainboard_silicon_init_params argument
Use FSPS_UPD instead of FSP_S_CONFIG as argument as already done on xeon_sp and denverton_ns. This allows to set test config UPDs from mainboard code as well. Change-Id: I6d67264e22df32b9210ce88b99d6a7a4f6b97ffb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c4
-rw-r--r--src/soc/intel/cannonlake/include/soc/ramstage.h2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 9b28d3d795..73b1bb53ed 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -143,7 +143,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Load VBT before devicetree-specific config. */
params->GraphicsConfigPtr = (uintptr_t)vbt_get();
- mainboard_silicon_init_params(params);
+ mainboard_silicon_init_params(supd);
const struct soc_power_limits_config *soc_config;
soc_config = &config->power_limits_config;
@@ -527,7 +527,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
}
/* Mainboard GPIO Configuration */
-__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+__weak void mainboard_silicon_init_params(FSPS_UPD *supd)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h
index 96b11298a7..ff4fd59f8c 100644
--- a/src/soc/intel/cannonlake/include/soc/ramstage.h
+++ b/src/soc/intel/cannonlake/include/soc/ramstage.h
@@ -9,7 +9,7 @@
#include "../../chip.h"
-void mainboard_silicon_init_params(FSP_S_CONFIG *params);
+void mainboard_silicon_init_params(FSPS_UPD *supd);
void soc_init_pre_device(void *chip_info);
#endif