diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-13 13:05:26 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-10 07:20:38 +0000 |
| commit | 06d224f65ee265f724f915dcbab0486773b7c6da (patch) | |
| tree | fd12cea016d3cf6cffc4e479f5c08795b42262c8 /src/soc/intel/cannonlake | |
| parent | 082f0b94ee1a6a6a06c6c6315c815b0c16274281 (diff) | |
nb/intel/x4x: Correct DDR3 turnaround table
Comparing against MRC, looks like the values for TA3 and TA4 are
backwards. All of them. Thus, correct the tables accordingly.
Tested on Acer G43T-AM3, DDR3-1066 and CL = 8 now works.
Change-Id: I2c99502b8f105c77098c888b024a4c3c2c8877d4
Tested-by: Michael Büchler <michael.buechler@posteo.net>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49388
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Büchler <michael.buechler@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
0 files changed, 0 insertions, 0 deletions