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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-16 19:52:32 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-04-06 06:56:01 +0000 |
| commit | 61469c7a35281b886692db6fc7e1b7114aca4807 (patch) | |
| tree | 9c4bb591b3dfa97c672811d122dd6baa792b67aa /src/soc/intel/cannonlake/uart.c | |
| parent | 71491a617661a04dc958f1bb1fe700c5b778129a (diff) | |
mb/ocp/tiogapass: correct "POST complete" pad initial value
On OCP Tioga Pass the pad GPP_B20 is used as output for signalling "POST
complete" to the BMC. According to the schematics and the code in
`ramstage.c`, the signal is active-low. There is an external pull-up
resistor.
To make the signalling work as it should, set the initial output value
to `high`.
Change-Id: I82fbda1caba9163ba3b2e38f494a0cefa27e657f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48670
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/uart.c')
0 files changed, 0 insertions, 0 deletions