diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-02-20 11:49:45 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-02-22 09:56:37 +0000 |
| commit | e83d057c3ec3b9a34503008439275777849c0c6a (patch) | |
| tree | ab7e04792cf134c70382f1356b7486abfde10366 /src/soc/intel/cannonlake/include | |
| parent | f9eaede51848d28214b47ade110b20ceac8a53e2 (diff) | |
soc/intel/cannonlake: Add provision to make CSME function disable in SMM mode
TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree.
Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23824
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pcr_ids.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h index b77eab831b..04ea147f38 100644 --- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h +++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h @@ -25,6 +25,7 @@ #define PID_GPIOCOM0 0x6e #define PID_DMI 0x88 #define PID_PSTH 0x89 +#define PID_CSME0 0x90 #define PID_ISCLK 0xad #define PID_PSF1 0xba #define PID_PSF2 0xbb |