From e83d057c3ec3b9a34503008439275777849c0c6a Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 20 Feb 2018 11:49:45 +0530 Subject: soc/intel/cannonlake: Add provision to make CSME function disable in SMM mode TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree. Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/23824 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/include/soc/pcr_ids.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/cannonlake/include') diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h index b77eab831b..04ea147f38 100644 --- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h +++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h @@ -25,6 +25,7 @@ #define PID_GPIOCOM0 0x6e #define PID_DMI 0x88 #define PID_PSTH 0x89 +#define PID_CSME0 0x90 #define PID_ISCLK 0xad #define PID_PSF1 0xba #define PID_PSF2 0xbb -- cgit v1.2.3