diff options
| author | Jeremy Soller <jeremy@system76.com> | 2020-12-29 11:17:28 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-21 11:01:08 +0000 |
| commit | 98d580b8fbd2cf9ccafc2dd0ad48ae7d5ba86186 (patch) | |
| tree | 3e0c7aa140eb8c13c934ab0bc371f2674e95a307 /src/soc/intel/cannonlake/include | |
| parent | 3b6b9c7b783f2005952c1521dba30fd5b598e68e (diff) | |
soc/intel/cannonlake: Allow RP#1 usage for ClkSrc
0 is converted to not used, so use a special value to allow using PCIe
root port #1.
Change-Id: I2d64afc9bb4627913492edad8f36566e7fb18166
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pch.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h index 0fbb98533a..e4fd36de33 100644 --- a/src/soc/intel/cannonlake/include/soc/pch.h +++ b/src/soc/intel/cannonlake/include/soc/pch.h @@ -10,5 +10,7 @@ #define PCIE_CLK_NOTUSED 0xFF #define PCIE_CLK_LAN 0x70 #define PCIE_CLK_FREE 0x80 +/* Converted to 0, allows 0 to be notused */ +#define PCIE_CLK_RP0 0xFE #endif |