From 98d580b8fbd2cf9ccafc2dd0ad48ae7d5ba86186 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Tue, 29 Dec 2020 11:17:28 -0700
Subject: soc/intel/cannonlake: Allow RP#1 usage for ClkSrc

0 is converted to not used, so use a special value to allow using PCIe
root port #1.

Change-Id: I2d64afc9bb4627913492edad8f36566e7fb18166
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
---
 src/soc/intel/cannonlake/include/soc/pch.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/soc/intel/cannonlake/include')

diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h
index 0fbb98533a..e4fd36de33 100644
--- a/src/soc/intel/cannonlake/include/soc/pch.h
+++ b/src/soc/intel/cannonlake/include/soc/pch.h
@@ -10,5 +10,7 @@
 #define PCIE_CLK_NOTUSED		0xFF
 #define PCIE_CLK_LAN			0x70
 #define PCIE_CLK_FREE			0x80
+/* Converted to 0, allows 0 to be notused */
+#define PCIE_CLK_RP0			0xFE
 
 #endif
-- 
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