diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-09-09 09:37:06 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-09 13:31:36 +0000 |
| commit | 13e902d5718ef57571ec3c0e4f08c9368b6766cc (patch) | |
| tree | 50a6fd9d167e3d175e829310da120eb881657239 /src/soc/intel/cannonlake/graphics.c | |
| parent | aa8d7721d400c20b73a1de8036d45654bdc625ee (diff) | |
soc/intel/cannonlake: Allow coreboot to handle SPI lockdown
This patch disables FSP-S SPI lockdown UPDs and lets coreboot perform
SPI lockdown (i.e.flash register DLOCK, FLOCKDN, and WRSDIS before
end of post) in ramstage.
BUG=b:138200201
TEST=FSP debug build suggests those UPDs are disable now.
Change-Id: Id7a6b9859e058b9f1ec1bd45d2c388c02b8ac18c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src/soc/intel/cannonlake/graphics.c')
0 files changed, 0 insertions, 0 deletions