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| author | Shuo Liu <shuo.liu@intel.com> | 2024-06-19 06:48:45 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-06-28 11:27:41 +0000 |
| commit | 2eb9d5ed62d3c3a4484c686af12d29a390ccf963 (patch) | |
| tree | 103455b274fda0d467be62b3401fcb27c9a9445f /src/soc/intel/cannonlake/gpio_cnp_h.c | |
| parent | 0a6f5188e80d888529e2067d02add19f65cb013c (diff) | |
soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC
For Gen1 SoCs, the range starting from the end of VTd BAR to the end
of 32-bit domain MMIO resource window is reserved for unknown devices.
Get them reserved.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ie133fe3173ce9696769c7247bd2524c7b21b1cf8
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/cannonlake/gpio_cnp_h.c')
0 files changed, 0 insertions, 0 deletions