diff options
author | Subrata Banik <subratabanik@google.com> | 2022-01-03 18:29:05 +0000 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-17 15:49:24 +0000 |
commit | 805956bce30090ea8c047f3a5c102f38c47388ee (patch) | |
tree | 63b0fc35b6859c79da3f3c6fe5cc917907db774f /src/soc/intel/cannonlake/fsp_params.c | |
parent | 53c7453ba1ecdcd8c862cc535be2ae4082a17bdd (diff) |
soc/intel/cnl: Use Kconfig to disable HECI1
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Cannon Lake
and ensures disable_heci1() is guarded against this config.
Also, makes dt CSE PCI device `on` by default.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/cannonlake/fsp_params.c')
-rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index fc12890410..af356d1985 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -587,7 +587,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Heci3Enabled = is_devfn_enabled(PCH_DEVFN_CSE_3); #if !CONFIG(HECI_DISABLE_USING_SMM) - params->Heci1Disabled = !is_devfn_enabled(PCH_DEVFN_CSE); + params->Heci1Disabled = CONFIG(DISABLE_HECI1_AT_PRE_BOOT); #endif params->Device4Enable = config->Device4Enable; |