diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2020-05-18 12:03:52 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-17 09:17:38 +0000 |
| commit | 9de8c8013b93c5e224e16c5514aacf4d761d6971 (patch) | |
| tree | b4fc2de021222ca1cedb6543b92f46ea3aa54e9e /src/soc/intel/cannonlake/chip.h | |
| parent | 802cbee78956afa6fad209d279f6d99e33ea85dd (diff) | |
soc/intel/cannonlake: Use table instead of switch-case
This makes future changes easier to review.
Change-Id: I5d67801a46a1613fbc7f813e94933fa30c1b92df
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 4b48a2184a..3ebbc5e38d 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -28,6 +28,12 @@ #define SOC_INTEL_CML_UART_DEV_MAX 3 #define SOC_INTEL_CML_SATA_DEV_MAX 8 +enum chip_pl2_4_cfg { + baseline, + performance, + value_not_set /* vr_config internal use only */ +}; + struct soc_intel_cannonlake_config { /* Common struct containing soc config data required by common code */ @@ -242,10 +248,7 @@ struct soc_intel_cannonlake_config { * Performance: Maximum PLs for maximum performance. * Baseline: Baseline PLs for balanced performance at lower power. */ - enum { - baseline, - performance - } cpu_pl2_4_cfg; + enum chip_pl2_4_cfg cpu_pl2_4_cfg; /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, |