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| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-03-20 23:00:36 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-21 23:08:11 +0000 |
| commit | 94ab3a8631620f62058d84040b36d5096133e085 (patch) | |
| tree | 400fa1146b7ee3172070a2b46401aa6c88a44847 /src/soc/intel/cannonlake/chip.h | |
| parent | 452c41b6013478f5ada7e2678c5f744ef335872e (diff) | |
soc/intel/apl: Fix programming temporary MTRR on GLK
Programming MTRR happens later in the
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT codepath.
fast_spi_cache_bios_region() assumes an existing MTRR solution from
x86_setup_mtrrs_with_detect().
This fixes a problem introduced by 829e8e6 "soc/intel: Use common
codeflow for MP init".
Change-Id: I9b6130cf76317440ebe7a7a53e460e2b658d198e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73836
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
0 files changed, 0 insertions, 0 deletions