diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-10-04 13:43:47 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-18 19:46:10 +0000 |
| commit | 580bc412c7449a3592e80ac737c3492af6594dfa (patch) | |
| tree | 99907980f2b3c3ccd064a1894da90b81857ff97b /src/soc/intel/cannonlake/chip.h | |
| parent | 6cf501c3ae0278092cb76ccab015ad891af1fd48 (diff) | |
soc/intel/cannonlake: Update PCIE CLKREQ programing
UPD of PCI express clock request was updated in FSP 7.0.14.11,
change that in coreboot accordingly.
TEST=NONE
Change-Id: I2261deccfb489c0de577d580997744a484f07a04
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21878
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index ee908f0a4c..0cfa3c3eab 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -20,6 +20,7 @@ #include <intelblocks/gspi.h> #include <stdint.h> +#include <soc/pch.h> #include <soc/serialio.h> #include <soc/usb.h> #include <soc/vr_config.h> @@ -131,10 +132,15 @@ struct soc_intel_cannonlake_config { /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ uint8_t PchHdaAudioLinkHda; - /* Pcie Root Ports */ + /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - uint8_t PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS]; - uint8_t PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS]; + /* PCIe ouput clocks type to Pcie devices. + * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, + * 0xFF: not used */ + uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS]; + /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to + * clksrc. */ + uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]; /* SMBus */ uint8_t SmbusEnable; |