From 580bc412c7449a3592e80ac737c3492af6594dfa Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Wed, 4 Oct 2017 13:43:47 -0700 Subject: soc/intel/cannonlake: Update PCIE CLKREQ programing UPD of PCI express clock request was updated in FSP 7.0.14.11, change that in coreboot accordingly. TEST=NONE Change-Id: I2261deccfb489c0de577d580997744a484f07a04 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/21878 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/chip.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/cannonlake/chip.h') diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index ee908f0a4c..0cfa3c3eab 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -20,6 +20,7 @@ #include #include +#include #include #include #include @@ -131,10 +132,15 @@ struct soc_intel_cannonlake_config { /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ uint8_t PchHdaAudioLinkHda; - /* Pcie Root Ports */ + /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - uint8_t PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS]; - uint8_t PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS]; + /* PCIe ouput clocks type to Pcie devices. + * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, + * 0xFF: not used */ + uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS]; + /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to + * clksrc. */ + uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]; /* SMBus */ uint8_t SmbusEnable; -- cgit v1.2.3