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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-28 00:20:27 +0300
committerPatrick Georgi <pgeorgi@google.com>2019-10-02 11:21:10 +0000
commitd5f645c6cde230004ee5af6c62d451d1329928e9 (patch)
treeeb87509c96e5ee1fa26e87594c75a399d92402e2 /src/soc/intel/cannonlake/chip.c
parentd3d38c95b7c23c5bd455d35e1b5bef0bce7b2cc5 (diff)
soc/intel: Replace config_of_path() with config_of_soc()
The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure. Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h. Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.c')
-rw-r--r--src/soc/intel/cannonlake/chip.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index c0810fb2ea..0ce2f1aca7 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -170,7 +170,7 @@ void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads)
static void soc_fill_gpio_pm_configuration(void)
{
uint8_t value[TOTAL_GPIO_COMM];
- const config_t *config = config_of_path(SA_DEVFN_ROOT);
+ const config_t *config = config_of_soc();
if (config->gpio_override_pm)
memcpy(value, config->gpio_pm, sizeof(uint8_t) *