diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-10-12 17:59:02 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-18 01:13:51 +0000 |
| commit | 47569cf3a9be5d42a75c932d4148fa20c2d8b475 (patch) | |
| tree | b5c04ad951389a26e1eab016f5856eeb94e3ca2b /src/soc/intel/cannonlake/bootblock | |
| parent | d2cadc39f3894612ca7714d5a4712bd3c09f42de (diff) | |
soc/intel/cannonlake: Use EBDA area to store cbmem_top address
This patch uses BIOS EBDA area to store relevent details
like cbmem top during romstage after MRC init is done.
Also provide provision to use the same EBDA data across
various stages without reexecuting memory map algorithm.
BRANCH=none
BUG=b:63974384
TEST=Ensures HW based memmap algorithm is executing once in romstage
and store required data into EBDA for other stage to avoid redundant
calculation and get cbmem_top start from EBDA area.
Change-Id: I763ad8181396ea8d8c0d5cf088264791ba62dceb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/bootblock')
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/pch.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 0062c0d61c..091e6f7cbc 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -196,6 +196,4 @@ void pch_early_init(void) enable_rtc_upper_bank(); heci_init(HECI1_BASE_ADDRESS); - - clear_cbmem_top(); } |