diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-10-02 19:18:16 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-05 21:16:46 +0000 |
| commit | ae565463b6a7ad4edad76ff8e2f52e1176bf8783 (patch) | |
| tree | 4e605592b4d55dee959ff9c5a83a27dd10d01819 /src/soc/intel/cannonlake/acpi/southbridge.asl | |
| parent | d3476809955ffb69447cc02a5ea893ebd1da3eb3 (diff) | |
soc/intel/cannonlake: Add all the SOC level DSDT tables
Add all the SOC level DSDT tables, reference from skylake/kabylake.
Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/acpi/southbridge.asl')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/southbridge.asl | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 408c31bfde..fdba171ada 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -27,3 +27,21 @@ /* GPIO controller */ #include "gpio.asl" + +/* LPC 0:1f.0 */ +#include "lpc.asl" + +/* PCH HDA */ +#include "pch_hda.asl" + +/* Serial IO */ +#include "serialio.asl" + +/* SMBus 0:1f.3 */ +#include "smbus.asl" + +/* USB XHCI 0:14.0 */ +#include "xhci.asl" + +/* PCI _OSC */ +#include <soc/intel/common/acpi/pci_osc.asl> |