From ae565463b6a7ad4edad76ff8e2f52e1176bf8783 Mon Sep 17 00:00:00 2001
From: Lijian Zhao <lijian.zhao@intel.com>
Date: Mon, 2 Oct 2017 19:18:16 -0700
Subject: soc/intel/cannonlake: Add all the SOC level DSDT tables

Add all the SOC level DSDT tables, reference from skylake/kabylake.

Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/cannonlake/acpi/southbridge.asl | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

(limited to 'src/soc/intel/cannonlake/acpi/southbridge.asl')

diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index 408c31bfde..fdba171ada 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -27,3 +27,21 @@
 
 /* GPIO controller */
 #include "gpio.asl"
+
+/* LPC 0:1f.0 */
+#include "lpc.asl"
+
+/* PCH HDA */
+#include "pch_hda.asl"
+
+/* Serial IO */
+#include "serialio.asl"
+
+/* SMBus 0:1f.3 */
+#include "smbus.asl"
+
+/* USB XHCI 0:14.0 */
+#include "xhci.asl"
+
+/* PCI _OSC */
+#include <soc/intel/common/acpi/pci_osc.asl>
-- 
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