diff options
| author | praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> | 2018-09-27 00:00:13 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-17 12:16:47 +0000 |
| commit | 521e48c87da6c70644a03c7b5e77856a8e556e53 (patch) | |
| tree | 67db1fc9a1a1748f8977756d6138f4489ee7ab4d /src/soc/intel/cannonlake/Kconfig | |
| parent | e26c4a461132087930e7137043ab6ada1b4147c7 (diff) | |
soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions
- CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities.
- Add gpio pin definitions for CNP-H and related changes.
- Add gpio device name, host software ownership reg offset for CNP-H.
BUG: none
TEST: build and flash, boot to windows and yocto os on both CFL RVP8 &
RVP11 and verify power management, IO device functionalities
work fine.
Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/Kconfig')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dcec9bcc8f..e39aaadd7e 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -10,7 +10,7 @@ config SOC_INTEL_COFFEELAKE help Intel Coffeelake support -config CANNONLAKE_SOC_PCH_H +config SOC_INTEL_CANNONLAKE_PCH_H bool default n help @@ -165,7 +165,7 @@ config NHLT_DA7219 config MAX_ROOT_PORTS int - default 24 if CANNONLAKE_SOC_PCH_H + default 24 if SOC_INTEL_CANNONLAKE_PCH_H default 16 config SMM_TSEG_SIZE @@ -204,7 +204,7 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX config SOC_INTEL_I2C_DEV_MAX int - default 4 if CANNONLAKE_SOC_PCH_H + default 4 if SOC_INTEL_CANNONLAKE_PCH_H default 6 # Clock divider parameters for 115200 baud rate |