From 521e48c87da6c70644a03c7b5e77856a8e556e53 Mon Sep 17 00:00:00 2001 From: praveen hodagatta pranesh Date: Thu, 27 Sep 2018 00:00:13 +0800 Subject: soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions - CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities. - Add gpio pin definitions for CNP-H and related changes. - Add gpio device name, host software ownership reg offset for CNP-H. BUG: none TEST: build and flash, boot to windows and yocto os on both CFL RVP8 & RVP11 and verify power management, IO device functionalities work fine. Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e Signed-off-by: praveen hodagatta pranesh Reviewed-on: https://review.coreboot.org/28890 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/cannonlake/Kconfig') diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dcec9bcc8f..e39aaadd7e 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -10,7 +10,7 @@ config SOC_INTEL_COFFEELAKE help Intel Coffeelake support -config CANNONLAKE_SOC_PCH_H +config SOC_INTEL_CANNONLAKE_PCH_H bool default n help @@ -165,7 +165,7 @@ config NHLT_DA7219 config MAX_ROOT_PORTS int - default 24 if CANNONLAKE_SOC_PCH_H + default 24 if SOC_INTEL_CANNONLAKE_PCH_H default 16 config SMM_TSEG_SIZE @@ -204,7 +204,7 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX config SOC_INTEL_I2C_DEV_MAX int - default 4 if CANNONLAKE_SOC_PCH_H + default 4 if SOC_INTEL_CANNONLAKE_PCH_H default 6 # Clock divider parameters for 115200 baud rate -- cgit v1.2.3