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authorPatrick Georgi <pgeorgi@chromium.org>2015-04-29 20:44:06 +0200
committerPatrick Georgi <pgeorgi@google.com>2015-04-30 15:39:10 +0200
commitb5e1984594525878172fb17abf3939e71963a5ff (patch)
tree5367531fce0f2c9122b30ef1542c2e3d4df78e70 /src/soc/intel/broadwell
parente3f880e4d8c0a9c29451e08a1c30e4135af96076 (diff)
intel/broadwell: Don't select MONOTONIC_TIMER_MSR
That's a Haswell exclusive, used nowhere else, but confusing when hunting for the monotonic timer used on that SoC. Change-Id: I60ec523e54e5af0d2a418bcb9145de452a3a4ea9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10034 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell')
-rw-r--r--src/soc/intel/broadwell/Kconfig6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 91249ee007..695e495124 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -174,12 +174,6 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE
when the ramstage cache is invalid. If selected the system will
reset otherwise the ramstage will be reloaded from cbfs.
-config MONOTONIC_TIMER_MSR
- def_bool y
- select HAVE_MONOTONIC_TIMER
- help
- Provide a monotonic timer using the 24MHz MSR counter.
-
config INTEL_PCH_UART_CONSOLE
bool "Use Serial IO UART for console"
default n