diff options
| author | Tim Crawford <tcrawford@system76.com> | 2021-08-06 16:17:28 -0600 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-08-13 18:06:50 +0000 |
| commit | 8de2d591e2ba4d2dba2260cbf72391c582a4510d (patch) | |
| tree | c62892c03fe5cc7a11262425c967f461a6cb670b /src/soc/intel/broadwell | |
| parent | d0bd012b5e2462c8c654749da36b62512867e0ec (diff) | |
3rdparty/intel-microcode: Update submodule to 20210608 release
Update submodule pointer to include microcode for TGL and others.
Tested the following still boot:
- galp3-c (WHL-U): sig=0x806eb pf=0x80 revision=0xe9
- oryp5 (CFL-H): sig=0x906ea pf=0x20 revision=0xe9
- gaze15 (CML-H): sig=0xa0652 pf=0x20 revision=0xe9
coreboot reports the revision as -1 from what it actually is. i.e.,
these should report revision=0xea (and that is what Linux reports).
However, this behavior is not new.
Change-Id: I084ba67e8eaf7383f1c05fa5589b63c92ff900b1
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56861
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell')
0 files changed, 0 insertions, 0 deletions