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authorKyösti Mälkki <kyosti.malkki@gmail.com>2023-01-05 15:39:16 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2023-05-09 18:08:45 +0000
commit83faa5d804d183a26b0fa66b5d55bbe5f3b72c89 (patch)
tree9818e9b83a6e24884516182f20380850039bef86 /src/soc/intel/broadwell
parent923b8ec18085d9b03162a1aae8dfd3aeff2d4fa0 (diff)
mb/google,intel: Use common ChromeEC code for lid shutdown
Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74514 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/broadwell')
-rw-r--r--src/soc/intel/broadwell/pch/pmutil.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c
index 4ba30b4ec6..e310416eaa 100644
--- a/src/soc/intel/broadwell/pch/pmutil.c
+++ b/src/soc/intel/broadwell/pch/pmutil.c
@@ -11,6 +11,7 @@
#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
+#include <halt.h>
#include <console/console.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
@@ -421,6 +422,16 @@ int platform_is_resuming(void)
return acpi_sleep_from_pm1(inl(get_pmbase() + PM1_CNT)) == ACPI_S3;
}
+void poweroff(void)
+{
+ uint32_t pm1_cnt;
+
+ /* Go to S5 */
+ pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+ pm1_cnt |= (0xf << 10);
+ outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
+}
+
/* STM Support */
uint16_t get_pmbase(void)
{