diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-29 20:36:47 +0100 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-16 06:31:22 +0000 |
| commit | 54b5e20cf87855324403689f0f05fba16267b7c4 (patch) | |
| tree | de00ac0dd64fd733b4086e575a4865f83924d159 /src/soc/intel/broadwell | |
| parent | dc873cc0c6402f289f34090f0fdb34588a04a9c0 (diff) | |
soc/intel/broadwell: Drop unnecessary `sa_dev`
Change-Id: Icc70adb0c3527a082622fd0ab70888e6cdf6b0ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46982
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell')
| -rw-r--r-- | src/soc/intel/broadwell/northbridge.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index b9aeb388a1..5f7d43b76a 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -280,7 +280,6 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) uint64_t mc_values[NUM_MAP_ENTRIES]; unsigned long dpr_size = 0; u32 dpr_reg; - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* Read in the MAP registers and report their values. */ mc_read_map_entries(dev, &mc_values[0]); @@ -292,7 +291,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) * the DPR register reports the TOP of the region, which is the same * as TSEG base. The region size is reported in MiB in bits 11:4. */ - dpr_reg = pci_read_config32(sa_dev, DPR); + dpr_reg = pci_read_config32(dev, DPR); if (dpr_reg & DPR_EPM) { dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16; printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size); |