diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-03-06 23:17:33 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-04-22 17:55:08 +0200 |
| commit | bd74a4b2d25268f7035a4478da31f27baac2aecc (patch) | |
| tree | 56740c02fe396df8ccf9fc2e7401542deeebf453 /src/soc/intel/broadwell/stage_cache.c | |
| parent | cac50506238507328b8ea0f4abd458869803e6c2 (diff) | |
coreboot: common stage cache
Many chipsets were using a stage cache for reference code
or when using a relocatable ramstage. Provide a common
API for the chipsets to use while reducing code duplication.
Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc/intel/broadwell/stage_cache.c')
| -rw-r--r-- | src/soc/intel/broadwell/stage_cache.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c index cb34297cdd..346e673cf5 100644 --- a/src/soc/intel/broadwell/stage_cache.c +++ b/src/soc/intel/broadwell/stage_cache.c @@ -18,11 +18,11 @@ */ #include <cbmem.h> -#include <ramstage_cache.h> #include <soc/smm.h> +#include <stage_cache.h> #include <stdint.h> -struct ramstage_cache *ramstage_cache_location(long *size) +void stage_cache_external_region(void **base, size_t *size) { /* The ramstage cache lives in the TSEG region. * The top of ram is defined to be the TSEG base address. */ @@ -30,6 +30,6 @@ struct ramstage_cache *ramstage_cache_location(long *size) offset -= CONFIG_IED_REGION_SIZE; offset -= CONFIG_SMM_RESERVED_SIZE; + *base = (void *)(cbmem_top() + offset); *size = CONFIG_SMM_RESERVED_SIZE; - return (void *)(cbmem_top() + offset); } |