aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/broadwell/romstage
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-10-26 00:27:09 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2020-11-13 13:17:49 +0000
commit3bd017356a7766c4884e55a28ca481c8a9110ceb (patch)
tree3d9ebcf9af8d5cbf5c3c63b25ed3bc2800baf573 /src/soc/intel/broadwell/romstage
parenta0426267e330c60aa74528a06a0e130efe2ad32f (diff)
soc/intel/broadwell: Relocate CPU files
Change-Id: Ib2ddce78db21db9c8deac632a77ecd71eb9887c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46794 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/romstage')
-rw-r--r--src/soc/intel/broadwell/romstage/Makefile.inc2
-rw-r--r--src/soc/intel/broadwell/romstage/cpu.c32
2 files changed, 0 insertions, 34 deletions
diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc
index b77e7a579d..65cb9adee5 100644
--- a/src/soc/intel/broadwell/romstage/Makefile.inc
+++ b/src/soc/intel/broadwell/romstage/Makefile.inc
@@ -1,5 +1,3 @@
-romstage-y += ../../../../cpu/intel/car/romstage.c
-romstage-y += cpu.c
romstage-y += raminit.c
romstage-y += report_platform.c
romstage-y += romstage.c
diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/soc/intel/broadwell/romstage/cpu.c
deleted file mode 100644
index c9f70a85d1..0000000000
--- a/src/soc/intel/broadwell/romstage/cpu.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/cpu.h>
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <soc/cpu.h>
-#include <soc/msr.h>
-#include <soc/romstage.h>
-
-void set_max_freq(void)
-{
- msr_t msr, perf_ctl, platform_info;
-
- /* Check for configurable TDP option */
- platform_info = rdmsr(MSR_PLATFORM_INFO);
-
- if ((platform_info.hi >> 1) & 3) {
- /* Set to nominal TDP ratio */
- msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
- perf_ctl.lo = (msr.lo & 0xff) << 8;
- } else {
- /* Platform Info bits 15:8 give max ratio */
- msr = rdmsr(MSR_PLATFORM_INFO);
- perf_ctl.lo = msr.lo & 0xff00;
- }
-
- perf_ctl.hi = 0;
- wrmsr(IA32_PERF_CTL, perf_ctl);
-
- printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
- ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
-}