broadwell: ACPI, romstage, and other updates

broadwell: Add romstage usbdebug support
Reviewed-on: https://chromium-review.googlesource.com/199412
(cherry picked from commit 1050e7d3be6ec1e4fe5aa2df408f4bb6d33a42b5)

broadwell: Add romstage code to configure PCH UART for console
Reviewed-on: https://chromium-review.googlesource.com/199807
(cherry picked from commit ecebda4eb5d6fe58473d25c2898ba1a2eac0f39a)

broadwell: Expand the PCI device convenience macros
Reviewed-on: https://chromium-review.googlesource.com/199891
(cherry picked from commit f8c54c70f136cd2cb8f977bc25661974d7e529ad)

broadwell: Add ramstage driver for ADSP
Reviewed-on: https://chromium-review.googlesource.com/199892
(cherry picked from commit e8e986b0ba52bbfc9923d71009fbd31e749ca43f)

broadwell: Update ACPI devices
Reviewed-on: https://chromium-review.googlesource.com/201080
(cherry picked from commit 2446b35578eb36e0009415bec340059135751549)

broadwell: Reserve DPR region
Reviewed-on: https://chromium-review.googlesource.com/201081
(cherry picked from commit 8ecd9d2096db2bded6f27ef6ee9a9b39ce2dfec6)

broadwell: Remove old pei_data and add cpu function for romstage
Reviewed-on: https://chromium-review.googlesource.com/201690
(cherry picked from commit d206c9cdd69519d502a90bb0595f0e3a7cb50274)

broadwell: Fixes for graphics without executing VBIOS
Reviewed-on: https://chromium-review.googlesource.com/202356
(cherry picked from commit 0c031df1ce92c875e95ddfd3f026f649c342c7fa)

broadwell: Fix compilation failure when loglevel is lowered
Reviewed-on: https://chromium-review.googlesource.com/202357
(cherry picked from commit 708ce78b2bfae5664b1238e17b086c88cac55bdc)

broadwell: Disable GPIO controller interrupt
Reviewed-on: https://chromium-review.googlesource.com/203645
(cherry picked from commit 2d17e98eded5958258ba5c0abf600284d8d03af9)

broadwell: Add support for E0 stepping
Reviewed-on: https://chromium-review.googlesource.com/205160
(cherry picked from commit 802e9d371418cc7a7fc7af131d7e5dda0ae5b273)

broadwell: misc updates for CPU driver
Reviewed-on: https://chromium-review.googlesource.com/205161
(cherry picked from commit ea1d403817ee193648f2c119fd45894e32e57e97)

broadwell: Read power state earlier and store in romstage params
Reviewed-on: https://chromium-review.googlesource.com/208151
(cherry picked from commit b2198d71084ad3c1360a0bfedc46c8dd3825bd0e)

broadwell: Add parameters to pei_data structure
Reviewed-on: https://chromium-review.googlesource.com/208153
(cherry picked from commit 423fbf67e497a907fbc8e12caf2929d4951858af)

broadwell: Move platform report output after power state is read
Reviewed-on: https://chromium-review.googlesource.com/208213
(cherry picked from commit acedf4146bf9377133433046dae1fa9c8bc69d78)

Squashed 15 commits for broadwell support.

Change-Id: I87e320d3d5376b84dd9c146b0b833e5ce53244aa
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6982
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

1 files changed, 85 insertions, 0 deletions

diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c
new file mode 100644
index 0000000000..8214a8a116
--- /dev/null
+++ b/src/soc/intel/broadwell/romstage/uart.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/early_variables.h>
+#include <arch/io.h>
+#include <delay.h>
+#include <device/pci_def.h>
+#include <reg_script.h>
+#include <stdint.h>
+#include <uart8250.h>
+#include <broadwell/iobp.h>
+#include <broadwell/serialio.h>
+
+const struct reg_script uart_init[] = {
+	/* Set MMIO BAR */
+	REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE),
+	/* Enable Memory access and Bus Master */
+	REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER),
+	/* Initialize LTR */
+	REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_GEN,
+		      ~SIO_REG_PPR_GEN_LTR_MODE_MASK, 0),
+	REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST,
+		      ~(SIO_REG_PPR_RST_ASSERT), 0),
+	/* Take UART out of reset */
+	REG_MMIO_OR32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST,
+		     SIO_REG_PPR_RST_ASSERT),
+	/* Set M and N divisor inputs and enable clock */
+	REG_MMIO_WRITE32(CONFIG_TTYS0_BASE + SIO_REG_PPR_CLOCK,
+			SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE |
+			(SIO_REG_PPR_CLOCK_N_DIV << 16) |
+			(SIO_REG_PPR_CLOCK_M_DIV << 1)),
+	REG_SCRIPT_END
+};
+
+void pch_uart_init(void)
+{
+	/* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */
+	u32 gpiodf = 0x131f;
+	device_t dev;
+
+	/* Put UART in byte access mode for 16550 compatibility */
+	switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) {
+	case 0:
+		dev = PCH_DEV_UART0;
+		gpiodf |= SIO_IOBP_GPIODF_UART0_BYTE_ACCESS;
+		break;
+	case 1:
+		dev = PCH_DEV_UART1;
+		gpiodf |= SIO_IOBP_GPIODF_UART1_BYTE_ACCESS;
+		break;
+	default:
+		return;
+	}
+
+	/* Program IOBP GPIODF */
+	pch_iobp_update(SIO_IOBP_GPIODF, ~gpiodf, gpiodf);
+
+	/* Program IOBP CB000180h[5:0] = 111111b (undefined register) */
+	pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f);
+
+	/* Initialize chipset uart interface */
+	reg_script_run_on_dev(dev, uart_init);
+
+	/*
+	 * Perform standard UART initialization
+	 * Divisor 1 is 115200 BAUD
+	 */
+	uart8250_mem_init(CONFIG_TTYS0_BASE, 1);
+}