diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-22 16:02:25 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-15 17:56:56 +0000 |
| commit | 5bb15f1a4d18bafaf51b17fd9ea6d861f2b9ebd2 (patch) | |
| tree | 8bedf540cdcf995931cb65799c881ad9a697cf26 /src/soc/intel/broadwell/romstage/romstage.c | |
| parent | 56f768774a25320d738febf99c335abdb6eeafbe (diff) | |
soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
This puts the cache-as-ram init in the bootblock.
Before setting up cache as ram the microcode updates are applied.
This removes the possibility for a normal/fallback setup although
implementing this should be quite easy.
Setting up LPC in the bootblock to output console on SuperIOs is not
done in this patch, therefore BOOTBLOCK_CONSOLE is not yet selected.
Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/broadwell/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 25c47c62c2..54434a3153 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -67,9 +67,7 @@ void platform_enter_postcar(void) /* Entry from cpu/intel/car/romstage.c. */ void mainboard_romstage_entry(unsigned long bist) { - struct romstage_params rp = { - .bist = bist, - }; + struct romstage_params rp = { 0 }; post_code(0x30); |