diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 23:09:16 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-24 12:07:55 +0000 |
| commit | d0d528a92a3605accabc1bfe6ddd35fab232c29a (patch) | |
| tree | ead4a41c5f1f96efb1240f5495d5bbf7cd4e8b20 /src/soc/intel/broadwell/romstage.c | |
| parent | 24e4edb37696baa13dbf55724051f173224a0d28 (diff) | |
soc/intel/broadwell: Align raminit with Haswell
Rename and split functions to match what Haswell does.
Change-Id: I4f3e997dd934bdf7717a70603d9413eae93cf181
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/soc/intel/broadwell/romstage.c')
| -rw-r--r-- | src/soc/intel/broadwell/romstage.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index d33156e575..33b4e4a02a 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -2,6 +2,8 @@ #include <acpi/acpi.h> #include <arch/romstage.h> +#include <cbmem.h> +#include <cf9_reset.h> #include <console/console.h> #include <cpu/intel/haswell/haswell.h> #include <elog.h> @@ -67,10 +69,22 @@ void mainboard_romstage_entry(void) &power_state->hsio_checksum); /* Initialize RAM */ - raminit(&pei_data); + sdram_initialize(&pei_data); timestamp_add_now(TS_AFTER_INITRAM); + if (pei_data.boot_mode != ACPI_S3) { + cbmem_initialize_empty(); + } else if (cbmem_initialize()) { + printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); + /* Failed S3 resume, reset to come up cleanly */ + system_reset(); + } + + save_mrc_data(&pei_data); + + setup_sdram_meminfo(&pei_data); + romstage_handoff_init(power_state->prev_sleep_state == ACPI_S3); mainboard_post_raminit(power_state->prev_sleep_state == ACPI_S3); |