From d0d528a92a3605accabc1bfe6ddd35fab232c29a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 20 Jan 2021 23:09:16 +0100 Subject: soc/intel/broadwell: Align raminit with Haswell MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename and split functions to match what Haswell does. Change-Id: I4f3e997dd934bdf7717a70603d9413eae93cf181 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/49778 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/soc/intel/broadwell/romstage.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/broadwell/romstage.c') diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index d33156e575..33b4e4a02a 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -2,6 +2,8 @@ #include #include +#include +#include #include #include #include @@ -67,10 +69,22 @@ void mainboard_romstage_entry(void) &power_state->hsio_checksum); /* Initialize RAM */ - raminit(&pei_data); + sdram_initialize(&pei_data); timestamp_add_now(TS_AFTER_INITRAM); + if (pei_data.boot_mode != ACPI_S3) { + cbmem_initialize_empty(); + } else if (cbmem_initialize()) { + printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); + /* Failed S3 resume, reset to come up cleanly */ + system_reset(); + } + + save_mrc_data(&pei_data); + + setup_sdram_meminfo(&pei_data); + romstage_handoff_init(power_state->prev_sleep_state == ACPI_S3); mainboard_post_raminit(power_state->prev_sleep_state == ACPI_S3); -- cgit v1.2.3