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authorDuncan Laurie <dlaurie@chromium.org>2014-12-12 10:52:34 -0800
committerMarc Jones <marc.jones@se-eng.com>2015-04-15 21:46:07 +0200
commitab1e96a099c5197419308ed40d4fd06507b46ec2 (patch)
tree7cf1740a87a8ce22954fe75c1c003986b900473a /src/soc/intel/broadwell/ramstage.c
parentcb12f65931aa0bbc30c0e578c988452be70714ed (diff)
broadwell: Fixes for _SWS support
- These should be 64bit values so when they try to return -1 it is interpreted properly by the kernel. - The GPE value needs to be reset at the start so it does not return stale data from a previous resume. - If a GPE register is zero the value should only be updated if it has not yet found a set bit. BUG=chrome-os-partner:34532 BRANCH=samus,auron TEST=build and boot on samus, suspend/resume with various wake sources and ensure the reported _SWS values are correct in every case. Original-Change-Id: Ic6897f20ad2f321f3566694c032b75a3db120556 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/235012 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit be3c79b87b81563f744eb885708a52730debaccb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I801c6e4f90dde0f5f69685f987a9831ee5e99e4a Reviewed-on: http://review.coreboot.org/9699 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell/ramstage.c')
-rw-r--r--src/soc/intel/broadwell/ramstage.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c
index c9a422f8e4..eaa28d02f1 100644
--- a/src/soc/intel/broadwell/ramstage.c
+++ b/src/soc/intel/broadwell/ramstage.c
@@ -52,13 +52,15 @@ static void save_acpi_wake_source(global_nvs_t *gnvs)
gnvs->pm1i = -1;
/* Scan for first set bit in GPE registers */
+ gnvs->gpei = -1;
for (gpe_reg = 0; gpe_reg < GPE0_REG_MAX; gpe_reg++) {
u32 gpe = ps->gpe0_sts[gpe_reg] & ps->gpe0_en[gpe_reg];
int start = gpe_reg * GPE0_REG_SIZE;
int end = start + GPE0_REG_SIZE;
if (gpe == 0) {
- gnvs->gpei = end;
+ if (!gnvs->gpei)
+ gnvs->gpei = end;
continue;
}
@@ -73,7 +75,7 @@ static void save_acpi_wake_source(global_nvs_t *gnvs)
if (gnvs->gpei >= (GPE0_REG_MAX * GPE0_REG_SIZE))
gnvs->gpei = -1;
- printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %d GPE Index %d\n",
+ printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n",
gnvs->pm1i, gnvs->gpei);
}