soc/intel/broadwell: Consolidate SPD handling

Mainboards do not need to know about `pei_data` to tell northbridge code
where to find the SPD data. As done on Haswell, add the `mb_get_spd_map`
function and the `struct spd_info` type to retrieve SPD information from
mainboard code without having to use `pei_data` in said mainboard code.

Unlike Haswell MRC, Broadwell MRC uses all positions of the `spd_data`
array, not just the first. The placeholder SPD address for memory-down
seems to be different as well. Adapt the existing code to handle these
variations. Once complete, the abstraction layer for both MRC binaries
will have the same API.

Change-Id: I92a05003a319c354675368cae8e34980bd2f9e10
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

1 files changed, 15 insertions, 8 deletions

diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c
index 70f38043cd..686c782e2e 100644
--- a/src/soc/intel/broadwell/raminit.c
+++ b/src/soc/intel/broadwell/raminit.c
@@ -183,9 +183,9 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
  * 2 = disable dimm 1 on channel
  * 3 = disable dimm 0+1 on channel
  */
-static int make_channel_disabled_mask(const struct pei_data *pd, int ch)
+static int make_channel_disabled_mask(const struct spd_info *spdi, int ch)
 {
-	return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1);
+	return (!spdi->addresses[ch + ch] << 0) | (!spdi->addresses[ch + ch + 1] << 1);
 }
 
 void perform_raminit(const struct chipset_power_state *const power_state)
@@ -195,15 +195,22 @@ void perform_raminit(const struct chipset_power_state *const power_state)
 	struct pei_data pei_data = { 0 };
 
 	mainboard_fill_pei_data(&pei_data);
-	mainboard_fill_spd_data(&pei_data);
+
+	/* Obtain the SPD addresses from mainboard code */
+	struct spd_info spdi = { 0 };
+	mb_get_spd_map(&spdi);
+
+	if (CONFIG(HAVE_SPD_IN_CBFS))
+		copy_spd(&pei_data, &spdi);
 
 	/* Calculate unimplemented DIMM slots for each channel */
-	pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0);
-	pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1);
+	pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&spdi, 0);
+	pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&spdi, 1);
 
-	for (size_t i = 0; i < ARRAY_SIZE(pei_data.spd_addresses); i++) {
-		const uint8_t addr = pei_data.spd_addresses[i];
-		pei_data.spd_addresses[i] = addr == SPD_MEMORY_DOWN ? 0 : addr;
+	/* MRC expects left-aligned SMBus addresses, and 0 for memory-down */
+	for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++) {
+		const uint8_t addr = spdi.addresses[i];
+		pei_data.spd_addresses[i] = addr == SPD_MEMORY_DOWN ? 0 : addr << 1;
 	}
 
 	post_code(0x32);