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| author | Duncan Laurie <dlaurie@chromium.org> | 2014-08-26 13:47:18 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-27 06:24:20 +0100 |
| commit | edb55fc0ad232b666684977ba4f0fece4a858ffb (patch) | |
| tree | 0458a7dc7e26d760d414b55148a3b7a06ad36190 /src/soc/intel/broadwell/pcie.c | |
| parent | 55228ba4b41e820efea71a75c649a6dd29cc76d5 (diff) | |
broadwell: Fix GPE register addresses
This macro is incorrect and should be counting by dword instead of byte.
The effects of this were subtle: incorrect events in ELOG and hanging when
waking from USB input because PME_B0 was not disabled properly.
BUG=chrome-os-partner:31611
BRANCH=none
TEST=test wake from suspend with USB keyboard
Original-Change-Id: I7caf1d46283071787550a9765703897181774957
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214258
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 3cfc4a1812466cb1c1317b8f21321aafee623857)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I3e2f8190d824692ecb961615becf65319a6ffd8b
Reviewed-on: http://review.coreboot.org/8965
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/pcie.c')
0 files changed, 0 insertions, 0 deletions