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authorFelix Held <felix-coreboot@felixheld.de>2022-02-23 17:54:20 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-02-25 17:42:45 +0000
commit4b2464fc90d60f01b0d890e1a0dc6dcdbd119617 (patch)
treed6b552cd62528e73c38a3bfbd5088feb5b7e2170 /src/soc/intel/broadwell/pch/pcie.c
parent46a3a044adfc8ec15faafd529e27c718754861c3 (diff)
arch/x86: factor out and commonize HPET_BASE_ADDRESS definition
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000, so define this once in arch/x86 and include this wherever needed. The old AMD AGESA code in vendorcode that has its own definition is left unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common definition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc/intel/broadwell/pch/pcie.c')
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