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authorAngel Pons <th3fanbus@gmail.com>2020-10-25 21:11:58 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2020-11-13 12:02:43 +0000
commit56d37fbe6f65d6c92a082d30baf13e79331dcebd (patch)
tree86f387f2f117828125e840f808188ece09480d61 /src/soc/intel/broadwell/pch/acpi/gpio.asl
parente53dfe0cfba9a773079a7229b05ed4b4c5e9e3c4 (diff)
soc/intel/broadwell/pch/acpi: Clean up cosmetics
Use ASL 2.0 syntax where possible and uniformize code style to match the IASL disassembly. Some `Store` in gpio.asl change the binary if touched. Tested with BUILD_TIMELESS=1, Google Buddy does not change. Change-Id: Ic13c081fd7ee2212d851cc14263c1e2fd8970072 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46778 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/pch/acpi/gpio.asl')
-rw-r--r--src/soc/intel/broadwell/pch/acpi/gpio.asl27
1 files changed, 13 insertions, 14 deletions
diff --git a/src/soc/intel/broadwell/pch/acpi/gpio.asl b/src/soc/intel/broadwell/pch/acpi/gpio.asl
index cfe0aed0b2..6b20f2784d 100644
--- a/src/soc/intel/broadwell/pch/acpi/gpio.asl
+++ b/src/soc/intel/broadwell/pch/acpi/gpio.asl
@@ -15,7 +15,7 @@ Device (GPIO)
}
Name (_UID, 1)
- Name (RBUF, ResourceTemplate()
+ Name (RBUF, ResourceTemplate ()
{
DWordIo (ResourceProducer,
MinFixed, // IsMinFixed
@@ -41,10 +41,9 @@ Device (GPIO)
CreateDwordField (^RBUF, ^BAR0._MAX, BMAX)
CreateDwordField (^RBUF, ^BAR0._LEN, BLEN)
- Store (GPIO_BASE_SIZE, BLEN)
- Store (GPIO_BASE_ADDRESS, BMIN)
- Store (Subtract (Add (GPIO_BASE_ADDRESS,
- GPIO_BASE_SIZE), 1), BMAX)
+ BLEN = GPIO_BASE_SIZE
+ BMIN = GPIO_BASE_ADDRESS
+ BMAX = GPIO_BASE_ADDRESS + GPIO_BASE_SIZE - 1
Return (RBUF)
}
@@ -59,7 +58,7 @@ Device (GPIO)
Method (GWAK, 1, Serialized)
{
// Local0 = GPIO Base Address
- Store (And (GPBS, Not(0x1)), Local0)
+ Store (GPBS & ~1, Local0)
// Local1 = BANK, Local2 = OFFSET
Divide (Arg0, 32, Local2, Local1)
@@ -69,7 +68,7 @@ Device (GPIO)
//
// Local3 = GPIOBASE + GPIO_OWN(BANK)
- Store (Add (Local0, Multiply (Local1, 0x4)), Local3)
+ Store (Local0 + Local1 * 4, Local3)
// GPIO_OWN(BANK)
OperationRegion (IOWN, SystemIO, Local3, 4)
@@ -78,14 +77,14 @@ Device (GPIO)
}
// GPIO_OWN[GPIO] = 0 (ACPI)
- Store (And (GOWN, Not (ShiftLeft (0x1, Local2))), GOWN)
+ Store (GOWN & ~(1 << Local2), GOWN)
//
// Set ROUTE to SCI
//
// Local3 = GPIOBASE + GPIO_ROUTE(BANK)
- Store (Add (Add (Local0, 0x30), Multiply (Local1, 0x4)), Local3)
+ Store (Local0 + 0x30 + Local1 * 4, Local3)
// GPIO_ROUTE(BANK)
OperationRegion (IROU, SystemIO, Local3, 4)
@@ -94,14 +93,14 @@ Device (GPIO)
}
// GPIO_ROUTE[GPIO] = 0 (SCI)
- Store (And (GROU, Not (ShiftLeft (0x1, Local2))), GROU)
+ Store (GROU & ~(1 << Local2), GROU)
//
// Set GPnCONFIG to GPIO|INPUT|INVERT
//
// Local3 = GPIOBASE + GPnCONFIG0(GPIO)
- Store (Add (Add (Local0, 0x100), Multiply (Arg0, 0x8)), Local3)
+ Store (Local0 + 0x100 + Arg0 * 8, Local3)
// GPnCONFIG(GPIO)
OperationRegion (GPNC, SystemIO, Local3, 8)
@@ -118,8 +117,8 @@ Device (GPIO)
ISEN, 1, // SENSE: 0=ENABLE 1=DISABLE
}
- Store (0x1, GMOD) // GPIO
- Store (0x1, GIOS) // INPUT
- Store (0x1, GINV) // INVERT
+ GMOD = 1 // GPIO
+ GIOS = 1 // INPUT
+ GINV = 1 // INVERT
}
}