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authorAngel Pons <th3fanbus@gmail.com>2020-09-24 16:50:05 +0200
committerNico Huber <nico.h@gmx.de>2020-10-14 08:36:43 +0000
commit2ead36334050ac692e64adc59a97320d8792adcc (patch)
treeca32a3b422b2be28268a390f65fe00bdc575914e /src/soc/intel/broadwell/pch.c
parent9bf45b43ee81ceed6c6545c6ccfb791cc28c8993 (diff)
soc/intel/broadwell: Align cosmetics with Haswell/Lynx Point
Tested with BUILD_TIMELESS=1, Purism Librem 13v1 does not change. Change-Id: Icf41d9db20e492ec77a83f8413ac99a654d6c8ed Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45697 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/pch.c')
-rw-r--r--src/soc/intel/broadwell/pch.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c
index 479323dd56..2a27d92152 100644
--- a/src/soc/intel/broadwell/pch.c
+++ b/src/soc/intel/broadwell/pch.c
@@ -64,9 +64,7 @@ u32 pch_read_soft_strap(int id)
/* Put device in D3Hot Power State */
static void pch_enable_d3hot(struct device *dev)
{
- u32 reg32 = pci_read_config32(dev, PCH_PCS);
- reg32 |= PCH_PCS_PS_D3HOT;
- pci_write_config32(dev, PCH_PCS, reg32);
+ pci_or_config32(dev, PCH_PCS, PCH_PCS_PS_D3HOT);
}
/* RCBA function disable and posting read to flush the transaction */