broadwell: ACPI, romstage, and other updates

broadwell: Add romstage usbdebug support
Reviewed-on: https://chromium-review.googlesource.com/199412
(cherry picked from commit 1050e7d3be6ec1e4fe5aa2df408f4bb6d33a42b5)

broadwell: Add romstage code to configure PCH UART for console
Reviewed-on: https://chromium-review.googlesource.com/199807
(cherry picked from commit ecebda4eb5d6fe58473d25c2898ba1a2eac0f39a)

broadwell: Expand the PCI device convenience macros
Reviewed-on: https://chromium-review.googlesource.com/199891
(cherry picked from commit f8c54c70f136cd2cb8f977bc25661974d7e529ad)

broadwell: Add ramstage driver for ADSP
Reviewed-on: https://chromium-review.googlesource.com/199892
(cherry picked from commit e8e986b0ba52bbfc9923d71009fbd31e749ca43f)

broadwell: Update ACPI devices
Reviewed-on: https://chromium-review.googlesource.com/201080
(cherry picked from commit 2446b35578eb36e0009415bec340059135751549)

broadwell: Reserve DPR region
Reviewed-on: https://chromium-review.googlesource.com/201081
(cherry picked from commit 8ecd9d2096db2bded6f27ef6ee9a9b39ce2dfec6)

broadwell: Remove old pei_data and add cpu function for romstage
Reviewed-on: https://chromium-review.googlesource.com/201690
(cherry picked from commit d206c9cdd69519d502a90bb0595f0e3a7cb50274)

broadwell: Fixes for graphics without executing VBIOS
Reviewed-on: https://chromium-review.googlesource.com/202356
(cherry picked from commit 0c031df1ce92c875e95ddfd3f026f649c342c7fa)

broadwell: Fix compilation failure when loglevel is lowered
Reviewed-on: https://chromium-review.googlesource.com/202357
(cherry picked from commit 708ce78b2bfae5664b1238e17b086c88cac55bdc)

broadwell: Disable GPIO controller interrupt
Reviewed-on: https://chromium-review.googlesource.com/203645
(cherry picked from commit 2d17e98eded5958258ba5c0abf600284d8d03af9)

broadwell: Add support for E0 stepping
Reviewed-on: https://chromium-review.googlesource.com/205160
(cherry picked from commit 802e9d371418cc7a7fc7af131d7e5dda0ae5b273)

broadwell: misc updates for CPU driver
Reviewed-on: https://chromium-review.googlesource.com/205161
(cherry picked from commit ea1d403817ee193648f2c119fd45894e32e57e97)

broadwell: Read power state earlier and store in romstage params
Reviewed-on: https://chromium-review.googlesource.com/208151
(cherry picked from commit b2198d71084ad3c1360a0bfedc46c8dd3825bd0e)

broadwell: Add parameters to pei_data structure
Reviewed-on: https://chromium-review.googlesource.com/208153
(cherry picked from commit 423fbf67e497a907fbc8e12caf2929d4951858af)

broadwell: Move platform report output after power state is read
Reviewed-on: https://chromium-review.googlesource.com/208213
(cherry picked from commit acedf4146bf9377133433046dae1fa9c8bc69d78)

Squashed 15 commits for broadwell support.

Change-Id: I87e320d3d5376b84dd9c146b0b833e5ce53244aa
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6982
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

7 files changed, 146 insertions, 25 deletions

diff --git a/src/soc/intel/broadwell/broadwell/adsp.h b/src/soc/intel/broadwell/broadwell/adsp.h
new file mode 100644
index 0000000000..747a123579
--- /dev/null
+++ b/src/soc/intel/broadwell/broadwell/adsp.h
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_ADSP_H_
+#define _BROADWELL_ADSP_H_
+
+#define ADSP_PCI_IRQ			23
+#define ADSP_ACPI_IRQ			3
+#define  ADSP_ACPI_IRQEN		(1 << 3)
+
+#define ADSP_SHIM_BASE_LPT		0xe7000
+#define ADSP_SHIM_BASE_WPT		0xfb000
+#define  ADSP_SHIM_LTRC			0xe0
+#define   ADSP_SHIM_LTRC_VALUE		0x3003
+#define  ADSP_SHIM_IMC			0x28
+#define  ADSP_SHIM_IPCD			0x40
+
+#define ADSP_PCI_VDRTCTL0		0xa0
+#define  ADSP_VDRTCTL0_D3PGD_LPT	(1 << 1)
+#define  ADSP_VDRTCTL0_D3PGD_WPT	(1 << 0)
+#define  ADSP_VDRTCTL0_D3SRAMPGD_LPT	(1 << 2)
+#define  ADSP_VDRTCTL0_D3SRAMPGD_WPT	(1 << 1)
+#define ADSP_PCI_VDRTCTL1		0xa4
+#define ADSP_PCI_VDRTCTL2		0xa8
+#define  ADSP_VDRTCTL2_VALUE		0x00000fff
+
+#define ADSP_IOBP_VDLDAT1		0xd7000624
+#define  ADSP_VDLDAT1_VALUE		0x00040100
+#define ADSP_IOBP_VDLDAT2		0xd7000628
+#define  ADSP_IOBP_ACPI_IRQ3		0xd9d8
+#define  ADSP_IOBP_ACPI_IRQ3I		0xd8d9
+#define  ADSP_IOBP_ACPI_IRQ4		0xdbda
+#define ADSP_IOBP_PMCTL			0xd70001e0
+#define  ADSP_PMCTL_VALUE		0x3f
+#define ADSP_IOBP_PCICFGCTL		0xd7000500
+#define  ADSP_PCICFGCTL_PCICD		(1 << 0)
+#define  ADSP_PCICFGCTL_ACPIIE		(1 << 1)
+#define  ADSP_PCICFGCTL_SPCBAD		(1 << 7)
+
+#endif
diff --git a/src/soc/intel/broadwell/broadwell/cpu.h b/src/soc/intel/broadwell/broadwell/cpu.h
index 0f6f593736..312532d68a 100644
--- a/src/soc/intel/broadwell/broadwell/cpu.h
+++ b/src/soc/intel/broadwell/broadwell/cpu.h
@@ -36,6 +36,7 @@
 #define CPUID_HASWELL_HALO	0x40661
 #define CPUID_BROADWELL_C0	0x306d2
 #define CPUID_BROADWELL_D0	0x306d3
+#define CPUID_BROADWELL_E0	0x306d4
 
 /* CPU bus clock is fixed at 100MHz */
 #define CPU_BCLK		100
diff --git a/src/soc/intel/broadwell/broadwell/device_nvs.h b/src/soc/intel/broadwell/broadwell/device_nvs.h
index f10f28d35e..7dab40da6a 100644
--- a/src/soc/intel/broadwell/broadwell/device_nvs.h
+++ b/src/soc/intel/broadwell/broadwell/device_nvs.h
@@ -33,11 +33,12 @@
 #define SIO_NVS_UART0		5
 #define SIO_NVS_UART1		6
 #define SIO_NVS_SDIO		7
+#define SIO_NVS_ADSP		8
 
 typedef struct {
-	u8	enable[8];
-	u32	bar0[8];
-	u32	bar1[8];
+	u8	enable[9];
+	u32	bar0[9];
+	u32	bar1[9];
 } __attribute__((packed)) device_nvs_t;
 
 #endif
diff --git a/src/soc/intel/broadwell/broadwell/pci_devs.h b/src/soc/intel/broadwell/broadwell/pci_devs.h
index 9c3dd06640..76e3a688ed 100644
--- a/src/soc/intel/broadwell/broadwell/pci_devs.h
+++ b/src/soc/intel/broadwell/broadwell/pci_devs.h
@@ -20,6 +20,9 @@
 #ifndef _BROADWELL_PCI_DEVS_H_
 #define _BROADWELL_PCI_DEVS_H_
 
+#define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
+#define _PCH_DEVFN(slot,func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
+
 #if defined(__PRE_RAM__) || defined(__SMM__) || defined(__ROMCC__)
 #include <arch/io.h>
 #define _SA_DEV(slot)		PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
@@ -27,43 +30,90 @@
 #else
 #include <device/device.h>
 #include <device/pci_def.h>
-#define _SA_DEV(slot)		dev_find_slot(0, \
-					PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0))
-#define _PCH_DEV(slot,func)	dev_find_slot(0, \
-					PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func))
+#define _SA_DEV(slot)		dev_find_slot(0, _SA_DEVFN(slot))
+#define _PCH_DEV(slot,func)	dev_find_slot(0, _PCH_DEVFN(slot, func))
 #endif
 
 /* System Agent Devices */
 
 #define SA_DEV_SLOT_ROOT	0x00
+#define  SA_DEVFN_ROOT		_SA_DEVFN(ROOT)
+#define  SA_DEV_ROOT		_SA_DEV(ROOT)
+
 #define SA_DEV_SLOT_IGD		0x02
-#define SA_DEV_SLOT_MINIHD	0x03
+#define  SA_DEVFN_IGD		_SA_DEVFN(IGD)
+#define  SA_DEV_IGD		_SA_DEV(IGD)
 
-#define SA_DEV_ROOT		_SA_DEV(ROOT)
-#define SA_DEV_IGD		_SA_DEV(IGD)
-#define SA_DEV_MINIHD		_SA_DEV(MINIHD)
+#define SA_DEV_SLOT_MINIHD	0x03
+#define  SA_DEVFN_MINIHD	_SA_DEVFN(MINIHD)
+#define  SA_DEV_MINIHD		_SA_DEV(MINIHD)
 
 /* PCH Devices */
 
+#define PCH_DEV_SLOT_ADSP	0x13
+#define  PCH_DEVFN_ADSP		_PCH_DEVFN(ADSP, 0)
+#define  PCH_DEV_ADSP		_PCH_DEV(ADSP, 0)
+
 #define PCH_DEV_SLOT_XHCI	0x14
+#define  PCH_DEVFN_XHCI		_PCH_DEVFN(XHCI, 0)
+#define  PCH_DEV_XHCI		_PCH_DEV(XHCI, 0)
+
 #define PCH_DEV_SLOT_SIO	0x15
+#define  PCH_DEV_SDMA		_PCH_DEV(SIO, 0)
+#define  PCH_DEV_I2C0		_PCH_DEV(SIO, 1)
+#define  PCH_DEV_I2C1		_PCH_DEV(SIO, 2)
+#define  PCH_DEV_SPI0		_PCH_DEV(SIO, 3)
+#define  PCH_DEV_SPI1		_PCH_DEV(SIO, 4)
+#define  PCH_DEV_UART0		_PCH_DEV(SIO, 5)
+#define  PCH_DEV_UART1		_PCH_DEV(SIO, 6)
+#define  PCH_DEVFN_SDMA		_PCH_DEVFN(SIO, 0)
+#define  PCH_DEVFN_I2C0		_PCH_DEVFN(SIO, 1)
+#define  PCH_DEVFN_I2C1		_PCH_DEVFN(SIO, 2)
+#define  PCH_DEVFN_SPI0		_PCH_DEVFN(SIO, 3)
+#define  PCH_DEVFN_SPI1		_PCH_DEVFN(SIO, 4)
+#define  PCH_DEVFN_UART0	_PCH_DEVFN(SIO, 5)
+#define  PCH_DEVFN_UART1	_PCH_DEVFN(SIO, 6)
+
 #define PCH_DEV_SLOT_ME		0x16
+#define  PCH_DEVFN_ME		_PCH_DEVFN(ME, 0)
+#define  PCH_DEVFN_ME_2		_PCH_DEVFN(ME, 1)
+#define  PCH_DEVFN_ME_IDER	_PCH_DEVFN(ME, 2)
+#define  PCH_DEVFN_ME_KT	_PCH_DEVFN(ME, 3)
+#define  PCH_DEV_ME		_PCH_DEV(ME, 0)
+#define  PCH_DEV_ME_2		_PCH_DEV(ME, 1)
+#define  PCH_DEV_ME_IDER	_PCH_DEV(ME, 2)
+#define  PCH_DEV_ME_KT		_PCH_DEV(ME, 3)
+
+#define PCH_DEV_SLOT_SDIO	0x17
+#define  PCH_DEVFN_SDIO		_PCH_DEVFN(SDIO, 0)
+#define  PCH_DEV_SDIO		_PCH_DEV(SDIO, 0)
+
+#define PCH_DEV_SLOT_GBE	0x19
+#define  PCH_DEVFN_GBE		_PCH_DEVFN(GBE, 0)
+#define  PCH_DEV_GBE		_PCH_DEV(GBE, 0)
+
 #define PCH_DEV_SLOT_HDA	0x1b
+#define  PCH_DEVFN_HDA		_PCH_DEVFN(HDA, 0)
+#define  PCH_DEV_HDA		_PCH_DEV(HDA, 0)
+
 #define PCH_DEV_SLOT_PCIE	0x1c
+
 #define PCH_DEV_SLOT_EHCI	0x1d
-#define PCH_DEV_SLOT_LPC	0x1f
+#define  PCH_DEVFN_EHCI		_PCH_DEVFN(EHCI, 0)
+#define  PCH_DEV_EHCI		_PCH_DEV(EHCI, 0)
 
-#define PCH_DEV_XHCI		_PCH_DEV(XHCI, 0)
-#define PCH_DEV_UART0		_PCH_DEV(UART0, 0)
-#define PCH_DEV_UART1		_PCH_DEV(UART1, 0)
-#define PCH_DEV_ME		_PCH_DEV(ME, 0)
-#define PCH_DEV_HDA		_PCH_DEV(HDA, 0)
-#define PCH_DEV_EHCI		_PCH_DEV(EHCI, 0)
-#define PCH_DEV_LPC		_PCH_DEV(LPC, 0)
-#define PCH_DEV_IDE		_PCH_DEV(LPC, 1)
-#define PCH_DEV_SATA		_PCH_DEV(LPC, 2)
-#define PCH_DEV_SMBUS		_PCH_DEV(LPC, 3)
-#define PCH_DEV_SATA2		_PCH_DEV(LPC, 5)
-#define PCH_DEV_THERMAL		_PCH_DEV(LPC, 6)
+#define PCH_DEV_SLOT_LPC	0x1f
+#define  PCH_DEVFN_LPC		_PCH_DEVFN(LPC, 0)
+#define  PCH_DEVFN_IDE		_PCH_DEVFN(LPC, 1)
+#define  PCH_DEVFN_SATA		_PCH_DEVFN(LPC, 2)
+#define  PCH_DEVFN_SMBUS	_PCH_DEVFN(LPC, 3)
+#define  PCH_DEVFN_SATA2	_PCH_DEVFN(LPC, 5)
+#define  PCH_DEVFN_THERMAL	_PCH_DEVFN(LPC, 6)
+#define  PCH_DEV_LPC		_PCH_DEV(LPC, 0)
+#define  PCH_DEV_IDE		_PCH_DEV(LPC, 1)
+#define  PCH_DEV_SATA		_PCH_DEV(LPC, 2)
+#define  PCH_DEV_SMBUS		_PCH_DEV(LPC, 3)
+#define  PCH_DEV_SATA2		_PCH_DEV(LPC, 5)
+#define  PCH_DEV_THERMAL	_PCH_DEV(LPC, 6)
 
 #endif
diff --git a/src/soc/intel/broadwell/broadwell/pei_data.h b/src/soc/intel/broadwell/broadwell/pei_data.h
index f8e63069b3..07b04d24d4 100644
--- a/src/soc/intel/broadwell/broadwell/pei_data.h
+++ b/src/soc/intel/broadwell/broadwell/pei_data.h
@@ -31,7 +31,7 @@
 
 #include <types.h>
 
-#define PEI_VERSION 20
+#define PEI_VERSION 21
 
 #define ABI_X86 __attribute__((regparm(0)))
 
@@ -122,6 +122,8 @@ struct pei_data
 	int dq_pins_interleaved;
 	/* Limit DDR3 frequency */
 	int max_ddr3_freq;
+	/* Disable self refresh */
+	int disable_self_refresh;
 
 	/* USB port configuration */
 	struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
@@ -167,6 +169,9 @@ struct pei_data
 	const void *saved_data;
 	int saved_data_size;
 
+	/* Disable use of saved data (can be set by mainboard) */
+	int disable_saved_data;
+
 	/* Data from MRC that should be saved to flash */
 	void *data_to_save;
 	int data_to_save_size;
diff --git a/src/soc/intel/broadwell/broadwell/romstage.h b/src/soc/intel/broadwell/broadwell/romstage.h
index d48ec13106..d3702c7490 100644
--- a/src/soc/intel/broadwell/broadwell/romstage.h
+++ b/src/soc/intel/broadwell/broadwell/romstage.h
@@ -29,9 +29,12 @@ struct romstage_timestamps {
 	int count;
 };
 
+struct chipset_power_state;
+struct pei_data;
 struct romstage_params {
 	struct romstage_timestamps ts;
 	unsigned long bist;
+	struct chipset_power_state *power_state;
 	struct pei_data *pei_data;
 };
 
@@ -52,6 +55,7 @@ void set_max_freq(void);
 
 void systemagent_early_init(void);
 void pch_early_init(void);
+void pch_uart_init(void);
 void intel_early_me_status(void);
 
 void enable_smbus(void);
diff --git a/src/soc/intel/broadwell/broadwell/systemagent.h b/src/soc/intel/broadwell/broadwell/systemagent.h
index 27c06f7608..f95370b2b5 100644
--- a/src/soc/intel/broadwell/broadwell/systemagent.h
+++ b/src/soc/intel/broadwell/broadwell/systemagent.h
@@ -52,6 +52,10 @@
 #define  DEVEN_D1F1EN	(1 << 2)
 #define  DEVEN_D1F2EN	(1 << 1)
 #define  DEVEN_D0EN	(1 << 0)
+#define DPR		0x5c
+#define  DPR_EPM	(1 << 2)
+#define  DPR_PRS	(1 << 1)
+#define  DPR_SIZE_MASK	0xff0
 
 #define PAM0		0x80
 #define PAM1		0x81