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authorAngel Pons <th3fanbus@gmail.com>2020-10-26 00:32:42 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2020-11-13 13:23:33 +0000
commit1500dd081b386db9b03ff78e74831cf6c9f88ba7 (patch)
treecf6bfb7aa57e70d128ceaa3625cbe9782373d3b3 /src/soc/intel/broadwell/bootblock
parent3bd017356a7766c4884e55a28ca481c8a9110ceb (diff)
soc/intel/broadwell: Flatten northbridge folder structure
Having folders for bootblock and romstage is no longer necessary. Change-Id: I7d1f4063de6a1a1ff9ee7478e94f889a50102054 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46795 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/bootblock')
-rw-r--r--src/soc/intel/broadwell/bootblock/systemagent.c28
1 files changed, 0 insertions, 28 deletions
diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c
deleted file mode 100644
index 5edfaeecaf..0000000000
--- a/src/soc/intel/broadwell/bootblock/systemagent.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/bootblock.h>
-#include <device/pci_ops.h>
-#include <soc/pci_devs.h>
-#include <soc/systemagent.h>
-
-void bootblock_early_northbridge_init(void)
-{
- uint32_t reg;
-
- /*
- * The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
- * to true. That way all subsequent non-explicit config accesses use
- * MCFG. This code also assumes that bootblock_northbridge_init() is
- * the first thing called in the non-asm boot block code. The final
- * assumption is that no assembly code is using the
- * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
- *
- * The PCIEXBAR is assumed to live in the memory mapped IO space under
- * 4GiB.
- */
- reg = 0;
- pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
- reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
- pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
-}