soc/intel/broadwell: Add back support for EHCI debug setup

The EHCI debug device setup code was removed from broadwell in
commit 49ee5ef: http://review.coreboot.org/11874

However the generic device setup code is in the southbridge/common/intel
directory while broadwell is in the soc directory so this is not used.
Add it back to the broadwell soc to fix undefined reference compile
errors with 'pci_ehci_dbg_dev' and 'pci_ehci_dbg_enable'.

This was tested to compile and produce romstage and ramstage output on a
google/samus board.

Change-Id: Ia93825a1e21a770f6c82d0989cb97980a5c700d6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/12794
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index e10704b485..4da8c204df 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -60,6 +60,8 @@ ramstage-y += systemagent.c
 ramstage-y += tsc_freq.c
 romstage-y += tsc_freq.c
 smm-y      += tsc_freq.c
+romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c
+ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
 ramstage-y += ehci.c
 ramstage-y += xhci.c
 smm-y      += xhci.c