From 8d2b49f1f71a88aad29f3a5d919156e6b7f3b103 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 22 Dec 2015 17:15:29 -0800 Subject: soc/intel/broadwell: Add back support for EHCI debug setup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The EHCI debug device setup code was removed from broadwell in commit 49ee5ef: http://review.coreboot.org/11874 However the generic device setup code is in the southbridge/common/intel directory while broadwell is in the soc directory so this is not used. Add it back to the broadwell soc to fix undefined reference compile errors with 'pci_ehci_dbg_dev' and 'pci_ehci_dbg_enable'. This was tested to compile and produce romstage and ramstage output on a google/samus board. Change-Id: Ia93825a1e21a770f6c82d0989cb97980a5c700d6 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/12794 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/broadwell/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/broadwell/Makefile.inc') diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index e10704b485..4da8c204df 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -60,6 +60,8 @@ ramstage-y += systemagent.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c smm-y += tsc_freq.c +romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c +ramstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-y += ehci.c ramstage-y += xhci.c smm-y += xhci.c -- cgit v1.2.3