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authorDuncan Laurie <dlaurie@chromium.org>2015-01-15 15:42:43 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-04-10 20:16:30 +0200
commitf059b241ad1ebd6b2084578b9284a19d018e8800 (patch)
tree13175b038d5c2f15df63ee73360696cb9a7391d1 /src/soc/intel/broadwell/Kconfig
parentf9a6a82ea64074ba401213256011f4875b2763de (diff)
broadwell: Add function to apply PRR to a range of SPI flash
This function will use the next available/free protected range register to cover the specified region of flash and write protect it until the next reset. This will be used by the common MRC cache code to protect the RW_MRC_CACHE region after it is updated. In order to communicate to the common NVM code that this function is defined also enable CONFIG_MRC_SETTINGS_PROTECT variable. BUG=chrome-os-partner:28234 BRANCH=broadwell TEST=build and boot on samus Change-Id: I710c6a69f725479411ed978cc615e1bb78fb42b8 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 25365433be0f190e10a96d9946b8ea90c883b78a Original-Change-Id: I4a4cd27f9f4a94b9134dcba623f33b114299818f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241129 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9493 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/Kconfig')
-rw-r--r--src/soc/intel/broadwell/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 2e70f45eea..e14476abbd 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS
select BACKUP_DEFAULT_SMM_REGION
select CACHE_MRC_BIN
select CACHE_MRC_SETTINGS
+ select MRC_SETTINGS_PROTECT
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
select CACHE_ROM
select CAR_MIGRATION