broadwell: Preparations for building

Updated Intel Broadwell for differences in the source based on
the chromium tree. It is missing most of the recent updates
on coreboot.org.

- makefile changes for Elog and IDF tool
- kconfig changes for ME, ucode, and other updates
- update oprom flag
- update timestamp mechanism
- cbfs payload function is now generic

Change-Id: I82bd0792e9dcf81085246873164de6600528d6fe
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7939
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>

1 files changed, 58 insertions, 3 deletions

diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 019bed3299..b93216e034 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -30,6 +30,7 @@ config CPU_SPECIFIC_OPTIONS
 	select MMCONF_SUPPORT
 	select MMCONF_SUPPORT_DEFAULT
 	select RELOCATABLE_MODULES
+	select RELOCATABLE_RAMSTAGE
 	select REG_SCRIPT
 	select PARALLEL_MP
 	select PCIEXP_ASPM
@@ -39,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SMP
 	select SPI_FLASH
 	select SSE2
+	select SUPPORT_CPU_UCODE_IN_CBFS
 	select TSC_CONSTANT_RATE
 	select TSC_SYNC_MFENCE
 	select UDELAY_TSC
@@ -56,9 +58,6 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 	default "soc/intel/broadwell/bootblock/pch.c"
 
-config MICROCODE_INCLUDE_PATH
-	string
-	default "src/soc/intel/broadwell/microcode"
 
 config MMCONF_BASE_ADDRESS
 	hex
@@ -208,6 +207,62 @@ config SERIRQ_CONTINUOUS_MODE
 	help
 	  If you set this option to y, the serial IRQ machine will be
 	  operated in continuous mode.
+config HAVE_ME_BIN
+	bool "Add Intel Management Engine firmware"
+	default y
+	help
+	  The Intel processor in the selected system requires a special firmware
+	  for an integrated controller called Management Engine (ME). The ME
+	  firmware might be provided in coreboot's 3rdparty repository. If
+	  not and if you don't have the firmware elsewhere, you can still
+	  build coreboot without it. In this case however, you'll have to make
+	  sure that you don't overwrite your ME firmware on your flash ROM.
+
+config ME_BIN_PATH
+	string "Path to management engine firmware"
+	depends on HAVE_ME_BIN
+	default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"
+
+config HAVE_IFD_BIN
+	bool
+	default n
+
+config BUILD_WITH_FAKE_IFD
+	bool "Build with a fake IFD"
+	default y if !HAVE_IFD_BIN
+	help
+	  If you don't have an Intel Firmware Descriptor (ifd.bin) for your
+	  board, you can select this option and coreboot will build without it.
+	  Though, the resulting coreboot.rom will not contain all parts required
+	  to get coreboot running on your board. You can however write only the
+	  BIOS section to your board's flash ROM and keep the other sections
+	  untouched. Unfortunately the current version of flashrom doesn't
+	  support this yet. But there is a patch pending [1].
+
+	  WARNING: Never write a complete coreboot.rom to your flash ROM if it
+		   was built with a fake IFD. It just won't work.
+
+	  [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
+
+config IFD_BIOS_SECTION
+	depends on BUILD_WITH_FAKE_IFD
+	string
+	default ""
+
+config IFD_ME_SECTION
+	depends on BUILD_WITH_FAKE_IFD
+	string
+	default ""
+
+config IFD_PLATFORM_SECTION
+	depends on BUILD_WITH_FAKE_IFD
+	string
+	default ""
+
+config IFD_BIN_PATH
+	string "Path to intel firmware descriptor"
+	depends on !BUILD_WITH_FAKE_IFD
+	default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"
 
 config ME_MBP_CLEAR_LATE
 	bool "Defer wait for ME MBP Cleared"