mb/google,intel: Use common ChromeEC code for lid shutdown

Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74514
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>

1 files changed, 11 insertions, 0 deletions

diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c
index a880183b82..3efcc7b6de 100644
--- a/src/soc/intel/braswell/pmutil.c
+++ b/src/soc/intel/braswell/pmutil.c
@@ -10,6 +10,7 @@
 #include <device/mmio.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
+#include <halt.h>
 #include <console/console.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>
@@ -356,3 +357,13 @@ int platform_is_resuming(void)
 
 	return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
 }
+
+void poweroff(void)
+{
+	uint32_t pm1_cnt;
+
+	/* Go to S5 */
+	pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+	pm1_cnt |= (0xf << 10);
+	outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
+}