diff options
| author | zbao <fishbaozi@gmail.com> | 2015-06-17 20:03:29 -0400 |
|---|---|---|
| committer | Zheng Bao <zheng.bao@amd.com> | 2015-06-25 04:06:59 +0200 |
| commit | 3ad1f1ca5fb35d698359c88baaa57939a258639a (patch) | |
| tree | d10b232e21eb91e69f56b49e5be76b41fae4257e /src/soc/intel/braswell | |
| parent | 128043edeea673f87c8a5d6dbcaf9f728d6c0869 (diff) | |
amd/pi/hudson: Fill ROMSIG with 0xFF instead of 0
Besides the first five DWORDs, the offsets 0x40 & 0x41
are used to save SPI settings. They should only be 0xFF
for being written.
Other parts in ROMSIG are also changed to 0xFF for potential
requirement.
Change-Id: I61ea8295d5ee8ffbbd0cfcf9e4bece770d70e1f2
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/10651
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell')
0 files changed, 0 insertions, 0 deletions