fsp/gop: Add running the GOP to the choice of gfx init

The new config choice is called RUN_FSP_GOP. Some things had to happen
on the road:

  * Drop confusing config GOP_SUPPORT,
  * Add HAVE_FSP_GOP to chipsets that support it,
  * Make running the GOP an option for FSP2.0 by returning 0
    in random VBT getters.

Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 10 insertions, 16 deletions

diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 61f41edd2c..520253add0 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -45,6 +45,7 @@ config CPU_SPECIFIC_OPTIONS
 	select USE_GENERIC_FSP_CAR_INC
 	select HAVE_INTEL_FIRMWARE
 	select HAVE_SPI_CONSOLE_SUPPORT
+	select HAVE_FSP_GOP
 
 config VBOOT
 	select VBOOT_STARTS_IN_ROMSTAGE
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index abd64a5ec0..88d024243b 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -20,7 +20,7 @@ ramstage-y += cpu.c
 ramstage-$(CONFIG_ELOG) += elog.c
 ramstage-y += emmc.c
 ramstage-y += gpio.c
-ifeq ($(CONFIG_GOP_SUPPORT),n)
+ifneq ($(CONFIG_RUN_FSP_GOP),y)
 ramstage-y += gfx.c
 endif
 ramstage-y += gpio_support.c
@@ -59,7 +59,6 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/braswell
 
 CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR)
 
-ifneq ($(CONFIG_GOP_SUPPORT),y)
 ifneq ($(CONFIG_VGA_BIOS_FILE),)
 #we will assume that the vbios names will remain as they are now: vgabios.bin and vgabios_c0.bin
 BRASWELL_C0_VBIOS= $(subst .bin,_c0.bin,$(call strip_quotes,$(CONFIG_VGA_BIOS_FILE)))
@@ -67,8 +66,6 @@ BRASWELL_C0_VBIOS= $(subst .bin,_c0.bin,$(call strip_quotes,$(CONFIG_VGA_BIOS_FI
 cbfs-files-$(CONFIG_VGA_BIOS) += pci8086,22b1.rom
 pci8086,22b1.rom-file := $(BRASWELL_C0_VBIOS)
 pci8086,22b1.rom-type := optionrom
-
-endif # ifneq ($(CONFIG_GOP_SUPPORT),y)
 endif # ifneq ($(CONFIG_VGA_BIOS_FILE),)
 
 endif # ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 0acb90ce7b..7a518167b3 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -482,15 +482,15 @@ unsigned long southcluster_write_acpi_tables(device_t device,
 	current = acpi_write_hpet(device, current, rsdp);
 	current = acpi_align_current(current);
 
-#if CONFIG_GOP_SUPPORT
-	igd_opregion_t *opregion;
+	if (IS_ENABLED(CONFIG_RUN_FSP_GOP)) {
+		igd_opregion_t *opregion;
 
-	printk(BIOS_DEBUG, "ACPI:    * IGD OpRegion\n");
-	opregion = (igd_opregion_t *)current;
-	init_igd_opregion(opregion);
-	current += sizeof(igd_opregion_t);
-	current = acpi_align_current(current);
-#endif
+		printk(BIOS_DEBUG, "ACPI:    * IGD OpRegion\n");
+		opregion = (igd_opregion_t *)current;
+		init_igd_opregion(opregion);
+		current += sizeof(igd_opregion_t);
+		current = acpi_align_current(current);
+	}
 
 	ssdt2 = (acpi_header_t *)current;
 	memset(ssdt2, 0, sizeof(acpi_header_t));
@@ -544,7 +544,6 @@ __attribute__((weak)) void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
 {
 }
 
-#if CONFIG_GOP_SUPPORT
 /* Reading VBT table from flash */
 static void get_fsp_vbt(igd_opregion_t *opregion)
 {
@@ -615,4 +614,3 @@ int init_igd_opregion(igd_opregion_t *opregion)
 
 	return 0;
 }
-#endif
diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h
index ff3b1cd704..50d9577b16 100644
--- a/src/soc/intel/braswell/include/soc/acpi.h
+++ b/src/soc/intel/braswell/include/soc/acpi.h
@@ -20,10 +20,8 @@
 #include <arch/acpi.h>
 #include <soc/nvs.h>
 
-#if CONFIG_GOP_SUPPORT
 #include <fsp/gma.h>
 int init_igd_opregion(igd_opregion_t *igd_opregion);
-#endif
 
 void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
 void acpi_fill_in_fadt(acpi_fadt_t *fadt);